AQA A-Level Computer Science: Computer Architecture, Networking and Databases

AQA A-Level Computer Science demands a deep understanding of how computers work -- from the transistors inside a processor to the protocols that connect billions of devices across the internet. The topics of computer architecture, networking and databases form a major portion of the specification, and they are tested primarily on Paper 2. Unlike topics that can be revised through rote memorisation, these areas require you to understand systems, explain processes, and apply principles to unfamiliar scenarios.

This guide covers the core content you need across processor architecture, internal and external hardware, logic gates and Boolean algebra, networking, web technologies, and databases. Use it alongside targeted practice questions to build the precision and depth that examiners reward.

How These Topics Fit the AQA A-Level Structure

AQA A-Level Computer Science is assessed through two exams and a programming project:

• Paper 1 -- On-screen exam, 2 hours 30 minutes, 100 marks (40% of A-Level). This paper tests programming skills, computational thinking and problem-solving. You will write and analyse code in your chosen programming language.
• Paper 2 -- Written exam, 2 hours 30 minutes, 100 marks (40% of A-Level). This paper tests theoretical knowledge across the entire specification, including all the topics in this guide.
• Non-Exam Assessment (NEA) -- A programming project worth 75 marks (20% of A-Level). You design, implement and evaluate a computational solution to a problem.

Computer architecture, networking and databases are examined on Paper 2. Questions range from short-answer definitions and diagram labelling to extended-response questions where you must compare approaches, evaluate designs, or trace through processes step by step.

Processor Architecture

Von Neumann vs Harvard Architecture

The Von Neumann architecture uses a single memory store for both instructions and data. The processor fetches instructions and data along the same bus, which creates a bottleneck -- sometimes called the Von Neumann bottleneck -- because the processor cannot fetch an instruction and read data simultaneously.

The Harvard architecture uses separate memory stores for instructions and data, with independent buses for each. This allows the processor to fetch the next instruction while simultaneously reading or writing data, which increases throughput. Harvard architecture is commonly found in embedded systems and digital signal processors where predictable, high-speed execution is essential.

Most modern desktop processors use a modified Harvard architecture: they maintain separate Level 1 caches for instructions and data (Harvard-style) but use a unified main memory (Von Neumann-style). This gives the performance benefits of Harvard architecture while retaining the flexibility of a shared memory space.

CISC vs RISC

CISC (Complex Instruction Set Computer) processors have a large instruction set with many specialised instructions. A single CISC instruction can perform multiple low-level operations -- such as loading from memory, performing an arithmetic operation, and storing the result -- in one instruction cycle. x86 processors used in most desktops and laptops are CISC-based.

RISC (Reduced Instruction Set Computer) processors use a smaller set of simple instructions, each typically executing in a single clock cycle. RISC designs rely on the compiler to break complex operations into sequences of simple instructions. ARM processors, used in most smartphones and tablets, follow a RISC design.

Key comparison points for exam answers: RISC processors tend to be more power-efficient and easier to pipeline, while CISC processors can achieve more per instruction and may require fewer lines of machine code for the same task. In practice, modern CISC processors internally translate complex instructions into RISC-like micro-operations.

Pipelining

Pipelining allows a processor to overlap the stages of the fetch-decode-execute cycle. While one instruction is being executed, the next can be decoded, and the one after that can be fetched. This increases instruction throughput without increasing clock speed.

Pipeline hazards can reduce efficiency: data hazards occur when an instruction depends on the result of a previous instruction still in the pipeline; control hazards arise from branch instructions that change the flow of execution; structural hazards happen when two instructions need the same hardware resource at the same time.

Co-processors and GPUs

A co-processor is a supplementary processor designed to handle specific tasks, offloading work from the main CPU. A floating-point unit (FPU) is a classic example.

A GPU (Graphics Processing Unit) contains thousands of smaller cores optimised for parallel processing. While a CPU excels at sequential tasks with complex logic, a GPU excels at performing the same operation on many data points simultaneously. Beyond graphics rendering, GPUs are now widely used for machine learning, scientific simulation, and cryptocurrency mining -- any workload that benefits from massive parallelism.

Internal Hardware Components

The Bus System

A bus is a set of parallel wires that carry data between components. Three key buses connect the processor, memory and I/O controllers:

• Address bus -- Carries the memory address that the processor wants to read from or write to. It is unidirectional (processor to memory). The width of the address bus determines the maximum addressable memory: a 32-bit address bus can address 2^32 (approximately 4 billion) memory locations.
• Data bus -- Carries the actual data being transferred. It is bidirectional. The width of the data bus determines how much data can be transferred in a single operation.
• Control bus -- Carries control signals such as read/write signals, clock signals, interrupt requests and bus request/grant signals. Individual lines within the control bus may be unidirectional or bidirectional.

Registers

Registers are small, fast storage locations within the processor. The key registers you must know are:

• Program Counter (PC) -- Holds the address of the next instruction to be fetched. After each fetch, it is incremented (or updated by a branch instruction).
• Memory Address Register (MAR) -- Holds the address of the memory location currently being accessed. When the processor needs to read or write, the target address is placed in the MAR.
• Memory Data Register (MDR) -- Also called the Memory Buffer Register (MBR). Holds the data that has just been read from memory or the data that is about to be written to memory.
• Current Instruction Register (CIR) -- Holds the instruction that is currently being decoded and executed.
• Accumulator -- A general-purpose register used to store intermediate results of arithmetic and logic operations.

The Fetch-Decode-Execute Cycle

This is the fundamental operation cycle of a processor:

1. Fetch -- The address in the PC is copied to the MAR. The processor sends a read signal along the control bus. The instruction stored at that memory address is transferred along the data bus into the MDR. The instruction is then copied from the MDR to the CIR. The PC is incremented to point to the next instruction.
2. Decode -- The control unit decodes the instruction in the CIR, identifying the opcode (what operation to perform) and the operand (the data or address to operate on).
3. Execute -- The processor carries out the instruction. This might involve performing an arithmetic operation in the ALU, transferring data between registers and memory, or changing the value of the PC for a branch instruction.

This cycle repeats continuously. Each step is synchronised by the system clock. Exam questions often ask you to trace through the cycle for a specific instruction, so practise describing each stage precisely.

External Hardware

Input devices convert data from the outside world into a form the computer can process. Examples include keyboards, mice, microphones, scanners, and sensors. Output devices convert processed data into a human-readable or usable form -- monitors, printers, speakers, and actuators.

Secondary storage provides non-volatile, long-term data storage. The three main types are:

• Magnetic storage (e.g. hard disk drives) -- Uses magnetised regions on spinning platters. High capacity and low cost per gigabyte, but relatively slow access due to mechanical movement and vulnerable to physical damage.
• Optical storage (e.g. CDs, DVDs, Blu-ray) -- Uses laser light to read pits and lands on a disc surface. Portable and inexpensive, but limited capacity and slow write speeds.
• Solid-state storage (e.g. SSDs, USB flash drives) -- Uses NAND flash memory with no moving parts. Very fast access times, durable, and low power consumption, but higher cost per gigabyte than magnetic storage and a finite number of write cycles.

Logic Gates and Boolean Algebra

Core Logic Gates

You must know the six standard gates and their truth tables:

• AND -- Output is 1 only when all inputs are 1.
• OR -- Output is 1 when at least one input is 1.
• NOT -- Inverts the input. Output is 1 when input is 0, and vice versa.
• NAND -- The inverse of AND. Output is 0 only when all inputs are 1.
• NOR -- The inverse of OR. Output is 0 when at least one input is 1.
• XOR -- Output is 1 when inputs are different.

You should be able to draw circuit diagrams using standard gate symbols, trace inputs through multi-gate circuits, and construct truth tables for combined expressions.

Boolean Algebra and Simplification

Boolean algebra uses the operators AND (represented as a dot or multiplication), OR (represented as a plus), and NOT (represented as a bar over the variable or an apostrophe). Key laws include:

• Commutative laws: A + B = B + A; A . B = B . A
• Associative laws: (A + B) + C = A + (B + C); (A . B) . C = A . (B . C)
• Distributive laws: A . (B + C) = A . B + A . C
• Identity laws: A + 0 = A; A . 1 = A
• Complement laws: A + A' = 1; A . A' = 0
• Absorption laws: A + A . B = A; A . (A + B) = A

De Morgan's laws are particularly important for simplification:

• NOT (A AND B) = (NOT A) OR (NOT B)
• NOT (A OR B) = (NOT A) AND (NOT B)

These allow you to convert between AND/OR forms and are essential for simplifying complex Boolean expressions.

Karnaugh Maps

Karnaugh maps (K-maps) provide a visual method for simplifying Boolean expressions. You plot truth table outputs onto a grid where adjacent cells differ by only one variable. Groups of 1s that form rectangles of size 1, 2, 4, or 8 can be combined to eliminate variables. The result is a simplified sum-of-products expression.

For exam purposes, you will typically work with 2-variable, 3-variable, or 4-variable K-maps. Remember that the grid uses Gray code ordering (00, 01, 11, 10) so that adjacent cells differ by exactly one bit, and the map wraps around at the edges.

Flip-Flops, Half Adders and Full Adders

A flip-flop is a circuit that stores a single bit of data. It has two stable states and can be set or reset by input signals. Flip-flops are the building blocks of registers and memory.

A half adder adds two single-bit inputs and produces a sum and a carry. The sum is the XOR of the inputs; the carry is the AND of the inputs. However, it cannot account for a carry-in from a previous addition.

A full adder extends the half adder by accepting a carry-in bit. It can be constructed from two half adders and an OR gate. Full adders are chained together to build circuits capable of adding multi-bit binary numbers.

Networking

The TCP/IP Model

The TCP/IP model has four layers, each with specific responsibilities and protocols:

1. Application layer -- The layer closest to the user. Protocols here define how applications communicate. Key protocols include HTTP/HTTPS (web), FTP (file transfer), SMTP (sending email), IMAP/POP3 (receiving email), and DNS (domain name resolution).
2. Transport layer -- Manages end-to-end communication and ensures reliable data delivery. TCP (Transmission Control Protocol) provides reliable, ordered delivery with error checking and flow control. UDP (User Datagram Protocol) provides faster but unreliable delivery without guaranteed ordering -- suitable for live streaming and online gaming.
3. Internet layer -- Handles logical addressing and routing. IP (Internet Protocol) assigns addresses to devices and routes packets across networks. ICMP is used for error reporting and diagnostics (e.g. ping).
4. Network interface layer (also called the link layer) -- Deals with the physical transmission of data over the network medium. This includes Ethernet for wired connections and Wi-Fi (IEEE 802.11) for wireless connections. It handles MAC addressing and frame construction.

Packet Switching vs Circuit Switching

Packet switching breaks data into packets, each of which is routed independently across the network. Packets may take different paths and arrive out of order; the receiving device reassembles them. This is efficient because network resources are shared and there is no dedicated connection.

Circuit switching establishes a dedicated communication path between sender and receiver for the duration of the transmission. Traditional telephone networks use circuit switching. It guarantees consistent bandwidth but wastes resources if the line is idle during the connection.

The internet uses packet switching because it is more resilient (packets can be rerouted around failures) and more efficient for bursty data traffic.

IP Addressing and Subnetting

IPv4 addresses are 32-bit numbers, typically written in dotted decimal notation (e.g. 192.168.1.1). This gives approximately 4.3 billion unique addresses -- a number that has been exhausted due to the growth of the internet.

IPv6 addresses are 128-bit numbers, written in hexadecimal (e.g. 2001:0db8:85a3:0000:0000:8a2e:0370:7334). IPv6 provides a vastly larger address space and includes improvements such as simplified headers and built-in support for encryption.

Subnetting divides a network into smaller sub-networks. A subnet mask determines which portion of an IP address identifies the network and which identifies the host. For example, a subnet mask of 255.255.255.0 (/24 in CIDR notation) means the first 24 bits identify the network, leaving 8 bits for host addresses -- allowing up to 254 usable hosts on that subnet.

Security: Firewalls, Encryption, and Digital Signatures

A firewall monitors and filters incoming and outgoing network traffic based on predefined security rules. It can block unauthorised access, prevent certain types of traffic, and log suspicious activity. Firewalls can be hardware-based, software-based, or a combination.

Symmetric encryption uses the same key for both encryption and decryption. It is fast but presents the problem of securely distributing the shared key. AES is a widely used symmetric algorithm.

Asymmetric encryption uses a pair of keys -- a public key for encryption and a private key for decryption. Anyone can encrypt a message using the recipient's public key, but only the recipient's private key can decrypt it. RSA is a common asymmetric algorithm. Asymmetric encryption solves the key distribution problem but is computationally slower than symmetric encryption. In practice, many systems use a hybrid approach: asymmetric encryption to exchange a symmetric session key, then symmetric encryption for the actual data transfer.

Digital signatures verify the authenticity and integrity of a message. The sender hashes the message and encrypts the hash with their private key. The recipient decrypts the hash using the sender's public key and compares it with their own hash of the message. If the hashes match, the message has not been tampered with and the sender is authenticated.

Digital certificates are issued by a trusted Certificate Authority (CA) and bind a public key to an identity. They are used in HTTPS connections to verify that a website is genuine. The certificate contains the domain name, the public key, the issuing CA, and an expiry date, all signed by the CA's private key.

Client-Server and Peer-to-Peer Models

In the client-server model, a central server provides resources or services to multiple clients. The server manages data, handles requests, and enforces security. Examples include web servers, email servers, and database servers. This model is easy to manage centrally but creates a single point of failure and can become a bottleneck under heavy load.

In the peer-to-peer (P2P) model, all nodes act as both clients and servers. Each peer can share resources directly with other peers without a central server. File-sharing networks like BitTorrent use this model. P2P networks are resilient (no single point of failure) and scale well as more peers join, but they are harder to secure and manage.

The Internet and Web Technologies

The internet is a global network of interconnected networks. The World Wide Web is a service that runs on top of the internet, using HTTP/HTTPS to deliver web pages.

HTML (HyperText Markup Language) defines the structure and content of web pages using elements and tags. CSS (Cascading Style Sheets) controls the presentation and layout -- fonts, colours, spacing, and responsive design. JavaScript adds interactivity and dynamic behaviour to web pages, running in the user's browser.

APIs (Application Programming Interfaces) allow different software systems to communicate. Web APIs commonly use REST principles over HTTP, exchanging data in formats like JSON or XML. They enable web applications to retrieve data from servers, integrate with third-party services, and build modular architectures.

A web application combines front-end technologies (HTML, CSS, JavaScript) with server-side processing and database access. The server processes requests, applies business logic, queries a database, and returns dynamically generated content to the client.

Databases

Entity-Relationship Modelling

An entity-relationship (E-R) diagram models the data requirements of a system. Entities represent real-world objects or concepts (e.g. Student, Course). Attributes are properties of entities (e.g. StudentName, CourseTitle). Relationships describe how entities are connected.

Relationships have cardinality: one-to-one (e.g. one headteacher leads one school), one-to-many (e.g. one teacher teaches many students), or many-to-many (e.g. many students enrol on many courses). Many-to-many relationships must be resolved into two one-to-many relationships using a linking (junction) entity during normalisation.

Normalisation

Normalisation is the process of organising database tables to reduce data redundancy and avoid update anomalies:

• First Normal Form (1NF) -- Each column contains only atomic (indivisible) values, there are no repeating groups, and each row is unique (identified by a primary key).
• Second Normal Form (2NF) -- The table is in 1NF and every non-key attribute is fully functionally dependent on the entire primary key (not just part of a composite key). This step eliminates partial dependencies.
• Third Normal Form (3NF) -- The table is in 2NF and there are no transitive dependencies -- that is, no non-key attribute depends on another non-key attribute.

When answering normalisation questions in the exam, work through each stage methodically: identify the primary key, find partial and transitive dependencies, and split tables accordingly. Always show the resulting table structures with their keys clearly marked.

SQL

You must be able to write and interpret SQL statements:

SELECT -- Retrieves data from one or more tables:

SELECT StudentName, Grade FROM Students WHERE Grade = 'A';

INSERT -- Adds a new record:

INSERT INTO Students (StudentID, StudentName, Grade) VALUES (101, 'Alice', 'B');

UPDATE -- Modifies existing records:

UPDATE Students SET Grade = 'A' WHERE StudentID = 101;

DELETE -- Removes records:

DELETE FROM Students WHERE StudentID = 101;

JOIN -- Combines rows from two or more tables based on a related column:

SELECT Students.StudentName, Courses.CourseTitle
FROM Students
INNER JOIN Enrolments ON Students.StudentID = Enrolments.StudentID
INNER JOIN Courses ON Enrolments.CourseID = Courses.CourseID;

Keys and Referential Integrity

A primary key uniquely identifies each record in a table. It must be unique and cannot be null. A foreign key is a field in one table that references the primary key of another table, creating a link between the two tables.

Referential integrity is a constraint that ensures every foreign key value in a table matches an existing primary key value in the referenced table (or is null, if permitted). This prevents orphan records -- for example, an enrolment record that references a student who does not exist. Database management systems enforce referential integrity by preventing invalid inserts, updates, or deletions.

How These Topics Appear on Paper 2

Paper 2 questions on these topics range from short factual recall to extended analysis. Common question formats include:

• Describe questions asking you to explain a process (e.g. "Describe the stages of the fetch-decode-execute cycle") -- these require step-by-step precision.
• Compare questions asking you to evaluate two approaches (e.g. "Compare CISC and RISC architectures") -- structure your answer with clear points for each side and a conclusion.
• Apply questions asking you to normalise a given dataset, write SQL queries, simplify a Boolean expression, or trace through a logic circuit.
• Evaluate questions asking you to assess a network design, encryption method, or database schema -- these require you to weigh advantages and disadvantages in context.

For full marks on extended-response questions, use precise technical terminology, structure your answer logically, and always relate your points back to the specific scenario given in the question.

Prepare with LearningBro

These topics demand both understanding and practice. Test your knowledge with targeted questions on LearningBro:

• AQA A-Level Computer Science: Computer Architecture
• AQA A-Level Computer Science: Networking
• AQA A-Level Computer Science: Databases

Each course covers the specification content in detail with exam-style questions designed to build your confidence and identify gaps before Paper 2.