Input/Output Devices and Interfaces

This lesson covers how the processor communicates with peripheral devices — keyboards, displays, storage, sensors, and more. At A-Level you must understand I/O techniques, the role of device drivers, and how data is transferred between the CPU and peripherals.

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I/O Ports and Device Controllers

Every peripheral device connects to the CPU through an I/O port managed by a device controller (or I/O controller). The device controller:

• Translates between the device's own signalling format and the system bus format.
• Contains its own small set of registers (status register, control register, data register).
• Communicates with the CPU via the system bus.

┌─────┐     ┌──────────────┐     ┌──────────────┐
│ CPU │ ──→ │ Device       │ ──→ │ Peripheral   │
│     │ ←── │ Controller   │ ←── │ Device       │
└─────┘     └──────────────┘     └──────────────┘
         System Bus          Device-specific signals

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Methods of I/O Data Transfer

1. Programmed I/O (Polling)

The CPU continuously checks (polls) the device's status register to see if data is available or if the device is ready.

Step	Action
1	CPU sends a request to the device controller.
2	CPU repeatedly reads the status register in a loop.
3	When the status register indicates "ready", the CPU reads or writes data via the data register.

Advantages:

• Simple to implement.
• No additional hardware needed.

Disadvantages:

• Wasteful — the CPU is stuck in a busy-wait loop and cannot do other work while waiting.
• Slow if the device is much slower than the CPU (which is almost always the case).

2. Interrupt-Driven I/O

Instead of polling, the device sends an interrupt signal to the CPU when it is ready. The CPU can perform other tasks while waiting.

Step	Action
1	CPU sends a request to the device and continues executing other instructions.
2	When the device is ready, it sends an interrupt signal along the control bus.
3	The CPU pauses its current task, saves its state (pushes registers onto the stack).
4	The CPU executes the Interrupt Service Routine (ISR) to handle the data transfer.
5	The CPU restores its state and resumes the original task.

Advantages:

• CPU is not wasted — it can perform useful work while waiting.
• More efficient for slow devices (e.g. printers, keyboards).

Disadvantages:

• More complex hardware (interrupt controller) and software (ISR code).
• Interrupt overhead — saving and restoring state takes time.
• Must handle interrupt priorities when multiple devices interrupt simultaneously.

3. Direct Memory Access (DMA)

For high-speed, bulk data transfers (e.g. reading from a hard disk or network card), neither polling nor simple interrupts are efficient enough. DMA allows a dedicated DMA controller to transfer data directly between the device and main memory, without involving the CPU for each byte.