Von Neumann and Harvard Architecture

This lesson examines two foundational computer architectures — the Von Neumann model and the Harvard model — that underpin every modern processor. At A-Level you are expected to compare them in depth, explain why each is suited to particular use-cases, and discuss variants such as the Modified Harvard Architecture used in most desktop CPUs today.

The Von Neumann Architecture

The Von Neumann architecture was proposed by the mathematician John von Neumann in 1945. Its defining characteristic is the stored-program concept: both the program instructions and the data they operate on are held in the same memory and accessed via a single shared bus.

Key Components

Component	Role
Processor (CPU)	Fetches, decodes and executes instructions
Main memory (RAM)	Stores both program instructions and data in the same address space
System bus	A single set of buses (address bus, data bus, control bus) connecting CPU and memory
Input / Output	Peripheral devices connected through I/O controllers

How It Works

Instructions and data share the same memory and the same bus.
The CPU fetches an instruction from memory via the shared bus.
If data is needed, the CPU must wait until the instruction fetch is complete before fetching data — this creates a potential bottleneck known as the Von Neumann bottleneck.
Instructions are executed sequentially following the Fetch-Decode-Execute (FDE) cycle.

The Von Neumann Bottleneck

Because there is only one bus between the CPU and memory, the processor cannot fetch an instruction and read/write data at the same time. The bus becomes a bottleneck — the processor may be idle waiting for data, even though it could otherwise be doing useful work.

Exam Tip: The Von Neumann bottleneck is a favourite topic in A-Level exams. Be precise: the bottleneck arises because instructions and data share a single bus, not just because they share the same memory. State both facts for full marks.

The Harvard Architecture

The Harvard architecture uses physically separate memories and buses for instructions and data. It was originally developed at Harvard University for the Mark I relay computer.

Key Components

Component	Role
Processor (CPU)	Fetches, decodes and executes instructions
Instruction memory	Stores program instructions only
Data memory	Stores data only
Instruction bus	Dedicated bus connecting CPU to instruction memory
Data bus	Dedicated bus connecting CPU to data memory

Advantages over Von Neumann

No bottleneck — the CPU can fetch the next instruction from instruction memory at the same time as it reads or writes data, because there are two independent buses.
Different bus widths — the instruction bus and data bus can be optimised independently. For example, instructions might be 16 bits wide while data is 8 bits wide, reducing wasted bandwidth.
Reliability — programs cannot accidentally overwrite their own instructions, because the instruction memory can be made read-only.

Disadvantages

More complex and more expensive — two sets of buses and two memory systems increase silicon area and cost.
Under-utilisation — if one memory area (instruction or data) is full while the other has space, the unused space is wasted because the memories are separate.
Less flexible — code cannot be treated as data, making self-modifying programs impossible without special mechanisms.

Modified Harvard Architecture

Most modern desktop and laptop processors use a Modified Harvard architecture. This is essentially a Von Neumann design at the main-memory level (programs and data share RAM) but with separate Level 1 (L1) caches inside the CPU — one for instructions and one for data.

          CPU
    ┌──────────────────┐
    │  ┌─────┐ ┌─────┐ │
    │  │ L1-I │ │ L1-D │ │   ← Separate instruction and data caches (Harvard-style)
    │  └──┬──┘ └──┬──┘ │
    │     └───┬───┘     │
    │      L2 Cache     │
    └────────┬─────────┘
             │
      Unified Main Memory        ← Single shared memory (Von Neumann-style)

This hybrid gets the speed advantage of Harvard (simultaneous instruction and data access at the cache level) and the flexibility of Von Neumann (a single main memory for both programs and data).

Comparison Table

Feature	Von Neumann	Harvard	Modified Harvard
Memory for instructions and data	Shared	Separate	Shared main memory, split caches
Buses	Single shared bus	Separate instruction and data buses	Shared main bus, split at cache level
Von Neumann bottleneck	Yes	No	Reduced (mitigated by caches)
Cost / complexity	Lower	Higher	Moderate
Typical use	General-purpose PCs (historically)	DSPs, microcontrollers, embedded systems	Modern desktop/laptop CPUs
Self-modifying code	Possible	Not directly possible	Possible (via main memory)

Where Each Architecture Is Used

Von Neumann

General-purpose computers — desktops, laptops, servers (at the main-memory level).
Any system where flexibility and cost matter more than raw throughput.

Harvard

Digital Signal Processors (DSPs) — audio/video processing hardware that must stream data continuously while executing a fixed set of instructions.
Microcontrollers — many embedded controllers (e.g. PIC, AVR / Arduino) use a pure Harvard architecture with separate Flash (instructions) and SRAM (data).
Embedded real-time systems — where deterministic timing is critical.

Exam Tip: When asked to "state an application of the Harvard architecture", always give a concrete example (e.g. "digital signal processors used in audio processing" or "PIC microcontrollers used in embedded systems"). Vague answers such as "in small devices" will not score full marks.

Exam-Style Practice Points

Describe the Von Neumann architecture and explain the bottleneck. (4 marks)
Compare the Von Neumann and Harvard architectures. (6 marks — use a table!)
Explain why most modern CPUs use a Modified Harvard architecture rather than a pure Von Neumann or pure Harvard design. (4 marks)

Summary

Von Neumann: shared memory, shared bus, bottleneck, flexible, cheap.
Harvard: separate memories, separate buses, no bottleneck, faster for streaming workloads, more expensive.
Modified Harvard: best of both — split L1 caches for speed, unified main memory for flexibility.
Know real-world examples for each architecture.