Computer System Architecture

This lesson covers the internal architecture of a CPU (Central Processing Unit) as required by the AQA and OCR GCSE Computer Science specifications. You need to understand what the CPU is, why it matters, and how its components — the ALU, CU, and registers — work together to process instructions.

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What Is a CPU?

The CPU (Central Processing Unit) is the main processing component of a computer. It is often described as the "brain" of the computer because it carries out the instructions that make up a program. Every input you give, every calculation that is performed, and every output you receive passes through or is coordinated by the CPU.

Modern CPUs are fabricated on a single silicon chip and contain billions of transistors — tiny electronic switches that represent binary 1s and 0s.

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Von Neumann Architecture

Most modern computers follow the Von Neumann architecture, proposed by mathematician John von Neumann in 1945. The key features of this architecture are:

• Programs and data are stored together in main memory (RAM).
• Instructions are fetched from memory one at a time and executed in sequence.
• There is a single set of buses (data, address, and control) connecting the CPU to memory.

Feature	Description
Stored program concept	Instructions and data share the same memory
Sequential execution	Instructions are processed one after another
Single memory space	Both data and programs live in RAM
Buses	Data bus, address bus, and control bus connect components

Exam Tip: You may be asked to label a Von Neumann architecture diagram. Make sure you can identify the CPU, main memory, and the three buses.

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Components of the CPU

The diagram below summarises the three components inside the CPU and how they connect to main memory via the system bus.

graph TD
    A["CPU"] --> B["ALU (Arithmetic Logic Unit)"]
    A --> C["CU (Control Unit)"]
    A --> D["Registers"]
    D --> E["PC (Program Counter)"]
    D --> F["MAR (Memory Address Register)"]
    D --> G["MDR (Memory Data Register)"]
    D --> H["ACC (Accumulator)"]
    A --> I["System Bus"]
    I --> J["Main Memory (RAM)"]

The CPU contains three main components that you must know for GCSE:

1. The Arithmetic Logic Unit (ALU)

The ALU performs all arithmetic and logical operations within the CPU:

• Arithmetic operations: addition, subtraction, multiplication, division.
• Logical operations: comparisons such as equal to, greater than, less than, AND, OR, NOT.

Every calculation your computer makes — from adding up a spreadsheet to rendering a game frame — passes through the ALU.

2. The Control Unit (CU)

The Control Unit manages and coordinates the activities of the CPU:

• It fetches instructions from main memory.
• It decodes instructions to determine what operation is needed.
• It sends control signals to other components (ALU, memory, I/O devices) to tell them what to do.
• It controls the timing of operations using the system clock.

Think of the CU as a traffic controller — it does not process data itself but tells every other component when and how to act.

3. Registers

Registers are tiny, ultra-fast storage locations inside the CPU. They hold small amounts of data that are currently being used or processed. Because they are built directly into the CPU chip, registers are the fastest form of memory in a computer.

Key registers you should know:

Register	Full Name	Purpose
PC	Program Counter	Holds the memory address of the next instruction to be fetched
MAR	Memory Address Register	Holds the address of the memory location about to be read from or written to
MDR	Memory Data Register	Holds the data that has been fetched from memory or the data about to be written to memory
ACC	Accumulator	Stores the results of calculations performed by the ALU

Exam Tip: A very common exam question is: "What is the purpose of the program counter?" The answer: it holds the memory address of the next instruction to be fetched and executed.

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The System Bus

The CPU communicates with the rest of the computer via the system bus, which consists of three separate buses:

Bus	Function	Direction
Data bus	Carries data between the CPU, memory, and I/O devices	Bidirectional (data can flow both ways)
Address bus	Carries the memory address that the CPU wants to access	Unidirectional (CPU to memory only)
Control bus	Carries control signals (e.g., read, write, clock)	Bidirectional

How the Buses Work Together

1. The CPU places the address of the required data on the address bus.
2. A control signal is sent along the control bus to tell memory whether it is a read or write operation.
3. The data is transferred along the data bus between the CPU and memory.

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Putting It All Together

Below is a simplified text diagram of the Von Neumann architecture:

+---------------------------------------------+
|                     CPU                      |
|  +-------+   +-----------+   +----------+   |
|  |  CU   |   |    ALU    |   | Registers|   |
|  +-------+   +-----------+   |  PC      |   |
|                              |  MAR     |   |
|                              |  MDR     |   |
|                              |  ACC     |   |
|                              +----------+   |
+---------------------------------------------+
       |              |              |
  Control Bus     Data Bus     Address Bus
       |              |              |
+---------------------------------------------+
|              Main Memory (RAM)               |
+---------------------------------------------+

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Summary

• The CPU is the main processing unit, executing program instructions.
• The ALU handles arithmetic and logic.
• The CU fetches, decodes, and coordinates execution.
• Registers (PC, MAR, MDR, ACC) provide ultra-fast temporary storage inside the CPU.
• The system bus (data, address, control) connects the CPU to main memory and I/O.
• Most modern computers use the Von Neumann architecture where programs and data share the same memory.

Key Vocabulary: CPU, ALU, CU, register, program counter, MAR, MDR, accumulator, Von Neumann, data bus, address bus, control bus.

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Deeper Architecture: Buses, Word Size and Addressing

The word size of a CPU is the number of bits the processor handles in a single operation. A 32-bit CPU has a 32-bit word, a 64-bit CPU has a 64-bit word. The word size has far-reaching consequences:

• Data bus width is often equal to the word size. A 64-bit data bus can transfer 64 bits (8 bytes) per clock cycle; a 32-bit data bus can only transfer 4 bytes per cycle, so the 64-bit system moves data twice as fast at the same clock speed.
• Address bus width determines how much memory the CPU can address. An n-bit address bus can address 2^n locations. A 32-bit address bus can address 2^32 = 4,294,967,296 bytes (4 GiB); a 64-bit address bus can theoretically address 2^64 bytes (16 EiB), though real CPUs typically implement only 48 address lines.
• Registers are usually the word size as well, so a 64-bit CPU's accumulator holds 64 bits.

Worked Example: Address Bus Calculation

Question: A CPU has a 20-bit address bus and an 8-bit data bus. What is the maximum amount of memory it can address, and how many bits are transferred per bus cycle?

Working:

• Maximum addressable locations: 2^20 = 1,048,576 locations.
• If each location stores 1 byte, total memory = 1 MiB.
• Data bus carries 8 bits = 1 byte per cycle.

Clock Rate Conversions

Unit	Hertz	Meaning
1 kHz	10^3 Hz	One thousand cycles per second
1 MHz	10^6 Hz	One million cycles per second
1 GHz	10^9 Hz	One billion cycles per second

Worked Example: A CPU runs at 2.4 GHz. How many cycles does it complete in 5 ms?

Cycles = frequency x time = 2.4 x 10^9 x 5 x 10^-3 = 12,000,000 cycles (12 million).

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Pipelining and the Instruction Set

Modern CPUs improve throughput by pipelining: while one instruction is being executed, the next is being decoded and the one after is being fetched. This keeps every stage of the CPU busy and increases instructions per cycle. A simple pipeline might have four stages: Fetch, Decode, Execute, Write-back.

The instruction set is the complete set of machine-code instructions a particular CPU understands. Two families dominate:

Approach	Characteristics	Example
CISC (Complex Instruction Set Computer)	Many specialised instructions; variable length; used in desktop chips	Intel x86-64
RISC (Reduced Instruction Set Computer)	Small, uniform instructions; easier to pipeline; lower power	ARM (used in mobile, Apple Silicon)

Because each CPU family has its own instruction set, a program compiled for x86-64 will not run natively on ARM — it must be recompiled from source, or emulated.

Answering at different grade levels

Exam-style question (6 marks): Describe the role of the Control Unit, ALU and registers within the von Neumann architecture and explain how bus width affects performance.

Grades 3-4 answer: The CPU has a Control Unit that fetches instructions. The ALU does sums and logic. Registers hold small amounts of data. A wider bus can send more bits at once so the computer is faster.

Grades 5-6 answer: Under the von Neumann architecture, programs and data share one memory. The Control Unit fetches and decodes instructions and sends control signals; the ALU performs arithmetic and logical operations; registers (PC, MAR, MDR, ACC) store addresses and data inside the CPU. A wider data bus transfers more bits each clock cycle, and a wider address bus allows more memory to be addressed (2^n locations).

Grades 7-9 answer: In a von Neumann architecture, a single memory holds both instructions and data, accessed via shared buses. The Control Unit decodes the opcode from each instruction and issues timed control signals; the ALU executes arithmetic and logical micro-operations; the register file (PC, MAR, MDR, ACC, plus general-purpose registers) provides ultra-low-latency storage directly addressable by the instruction set. Bus width scales performance in two ways: the data bus width sets how many bits move per cycle (a 64-bit bus doubles the throughput of a 32-bit bus at the same clock speed), and the address bus width caps the physical address space at 2^n bytes. Narrow buses force multiple cycles per word, causing a bottleneck sometimes called the von Neumann bottleneck, which is partially mitigated by cache and pipelining.

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Further Architecture Concepts

Harvard vs von Neumann

Although GCSE focuses on von Neumann, you may see mention of Harvard architecture, in which instructions and data have separate memories and separate buses. Harvard architectures avoid the von Neumann bottleneck (instructions and data can be fetched simultaneously) and are common in embedded microcontrollers (for example ARM Cortex-M, AVR). Most desktop CPUs use a modified Harvard at the L1 cache level (separate instruction cache and data cache) while remaining von Neumann at the main-memory level.

Registers Beyond the Four You Must Know

Real CPUs have many registers. At GCSE you must know PC, MAR, MDR and ACC, but you should recognise that modern CPUs also include:

• Status register / flags — holds results such as carry, zero, overflow and negative flags from the last ALU operation.
• Current Instruction Register (CIR) — on some exam boards, the register that holds the instruction currently being decoded.
• General-purpose registers (R0..R15) — used by programs to hold variables for fast access.

Cores on a Chip

A modern microprocessor fabricates many cores on one die, each a complete CPU with its own ALU, CU, register file and L1/L2 caches, sharing an L3 cache and a memory controller. This lets the CPU execute many instruction streams truly in parallel. Interconnects (rings, meshes, crossbars) carry data between cores, cache slices and the memory controller, and the cache coherence protocol ensures that if core A updates a line in its L1 cache, core B's copy is invalidated so it cannot read stale data. Without coherence, multi-core programs would produce unpredictable results.

Bus Transactions in Practice

Every read or write to memory is a bus transaction: address and control signals are driven by the CPU; data flows either way. Wider data buses transfer more per transaction; faster clocks let more transactions complete per second. The memory controller arbitrates requests so no single component starves others. Recognising that all hardware components connect through the system bus is central to a strong GCSE answer on architecture.

AQA alignment: This content is aligned with AQA GCSE Computer Science (8525) specification — specifically section 3.4 Computer systems (3.4.1 Hardware and software, 3.4.2 Boolean logic [see separate lesson], 3.4.3 Software classification, 3.4.4 Systems architecture). Assessed on Paper 2.