CPU Architecture

This lesson covers the fundamental architectures that underpin modern processors, as required by the OCR H446 specification (section 1.1). You need to understand the Von Neumann model, the Harvard architecture, the purpose of key registers, and the role of the system buses.

The Von Neumann Model

The Von Neumann architecture was proposed by John von Neumann in 1945. Its key idea is the stored-program concept: both instructions and data are stored in the same memory and transferred over a single shared bus.

Key Components

Component	Role
Central Processing Unit (CPU)	Fetches, decodes and executes instructions
Main Memory (RAM)	Stores both program instructions and data in a single address space
System Bus	Connects the CPU to memory and I/O — comprises the address bus, data bus and control bus
Input/Output (I/O)	Peripheral devices connected through I/O controllers

The Von Neumann Bottleneck

Because instructions and data share a single bus, the CPU cannot fetch an instruction and read or write data at the same time. The bus becomes a bottleneck — the processor may sit idle while waiting for a data transfer to complete.

Exam Tip: When describing the Von Neumann bottleneck, state clearly that the limitation arises because instructions and data share a single bus, not just because they share the same memory. Examiners want both points.

The Harvard Architecture

The Harvard architecture uses physically separate memories and buses for instructions and data.

Key Components

Component	Role
Processor (CPU)	Fetches, decodes and executes instructions
Instruction Memory	Dedicated memory for storing program instructions
Data Memory	Dedicated memory for storing data
Instruction Bus	Dedicated bus between CPU and instruction memory
Data Bus	Dedicated bus between CPU and data memory

Advantages of Harvard over Von Neumann

No bottleneck — the CPU can fetch the next instruction while simultaneously reading or writing data, because the buses are independent.
Different bus widths — instruction and data buses can be optimised independently (e.g. 16-bit instructions, 8-bit data).
Improved reliability — programs cannot accidentally overwrite their own instructions if instruction memory is read-only.

Disadvantages of Harvard

More complex and expensive — two separate bus systems and memory modules increase cost and silicon area.
Wasted space — if instruction memory is full but data memory has spare capacity (or vice versa), the unused space cannot be shared.
Less flexible — code cannot easily be treated as data, so self-modifying programs are not directly possible.

Where Harvard Is Used

Harvard architecture is commonly found in:

Digital Signal Processors (DSPs) — used in audio and video processing where continuous data streaming alongside instruction execution is essential.
Microcontrollers — many embedded controllers such as PIC and AVR (Arduino) use Harvard architecture with separate Flash (instructions) and SRAM (data).
Embedded real-time systems — where predictable, deterministic timing is critical.

Modified Harvard Architecture

Most modern desktop and laptop CPUs use a Modified Harvard architecture. At the main-memory level, instructions and data share a single RAM (Von Neumann style). However, inside the CPU there are separate Level 1 (L1) caches for instructions and data (Harvard style).

          CPU
    +--------------------+
    |  +------+ +------+ |
    |  | L1-I | | L1-D | |   <-- Separate caches (Harvard-style)
    |  +--+---+ +--+---+ |
    |     +---+---+      |
    |      L2 Cache      |
    +--------+-----------+
             |
      Unified Main Memory         <-- Single shared memory (Von Neumann-style)

This hybrid approach gives the speed advantage of Harvard (simultaneous instruction and data access at the cache level) and the flexibility of Von Neumann (a single main memory for programs and data).

Comparison Table

Feature	Von Neumann	Harvard	Modified Harvard
Memory	Shared for instructions and data	Separate memories	Shared main memory, split caches
Buses	Single shared bus	Separate instruction and data buses	Shared main bus, split at cache level
Bottleneck	Yes	No	Reduced (mitigated by caches)
Cost / complexity	Lower	Higher	Moderate
Typical use	General-purpose PCs (historically)	DSPs, microcontrollers	Modern desktop/laptop CPUs

Key CPU Registers

The processor contains several special-purpose registers that play specific roles during instruction processing.

Register	Full Name	Purpose
PC	Program Counter	Holds the address of the next instruction to be fetched
MAR	Memory Address Register	Holds the address of the memory location about to be read from or written to
MDR	Memory Data Register	Holds the data that has just been read from memory, or the data about to be written to memory
CIR	Current Instruction Register	Holds the instruction currently being decoded and executed
ACC	Accumulator	A general-purpose register that holds the result of ALU operations

How the Registers Connect to the Buses

PC  ----> MAR ----> Address Bus ----> Memory
                                         |
MDR <----> Data Bus <------------------->|
 |
CIR <---- MDR
 |
Control Unit ----> Control Bus ----> Memory / I/O

The MAR is connected to the address bus (unidirectional — CPU to memory).
The MDR is connected to the data bus (bidirectional — data flows both ways).
The Control Unit sends signals along the control bus (e.g. read, write, interrupt).

The System Buses

A bus is a set of parallel wires that carries data, addresses or control signals between components.

Address Bus

Property	Detail
Direction	Unidirectional — from CPU to memory/I/O
Width	Determines the maximum addressable memory. A 32-bit address bus can address 2^32 = 4,294,967,296 locations (4 GB)
Purpose	Carries the address of the memory location or I/O port the CPU wants to access

Data Bus

Property	Detail
Direction	Bidirectional — data travels both from CPU to memory and from memory to CPU
Width	Determines how many bits can be transferred in a single operation. Common widths: 8, 16, 32, 64 bits
Purpose	Carries the actual data or instructions being transferred

Control Bus

Property	Detail
Direction	Bidirectional — some signals go from CPU to devices, others from devices to CPU
Key signals	Memory Read, Memory Write, I/O Read, I/O Write, Interrupt Request, Bus Request, Bus Grant, Clock
Purpose	Coordinates and controls the activities of all components connected to the bus

How Bus Width Affects Performance

Wider address bus = more memory locations can be addressed.
Wider data bus = more data can be transferred per cycle, increasing throughput.
Both contribute to overall system performance, but increasing bus width adds complexity and cost.

Exam Tip: A common exam question asks you to explain the effect of increasing the width of the address bus vs the data bus. Increasing the address bus width allows the CPU to address more memory locations. Increasing the data bus width allows the CPU to transfer more data per operation, improving throughput. State both effects precisely.

Worked Example

Question: A computer has a 24-bit address bus and a 16-bit data bus. Calculate the maximum addressable memory and the amount of data that can be transferred in one operation.

Answer:

Maximum addressable memory = 2^24 = 16,777,216 locations = 16 MB (if each location holds 1 byte)
Data transferred per operation = 16 bits = 2 bytes

Key Terms

Term	Definition
Stored-program concept	The idea that both instructions and data are stored in the same memory
Von Neumann bottleneck	The performance limitation caused by instructions and data sharing a single bus
Register	A small, fast storage location inside the CPU
Bus	A set of parallel wires connecting components for data, address or control signal transfer
Word size	The number of bits the CPU can process in a single operation, often matching the data bus width

Summary

The Von Neumann architecture stores instructions and data in the same memory with a single bus — simple but creates a bottleneck.
The Harvard architecture uses separate memories and buses for instructions and data — faster but more expensive.
Modified Harvard combines both: split L1 caches inside the CPU, unified main memory.
The PC, MAR, MDR, CIR and ACC are key registers with specific roles.
The three buses — address, data and control — connect the CPU to memory and I/O devices.