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This lesson covers the fundamental architectures that underpin modern processors, as required by the OCR H446 specification (section 1.1). You need to understand the Von Neumann model, the Harvard architecture, the purpose of key registers, and the role of the system buses.
The Von Neumann architecture was proposed by John von Neumann in 1945. Its key idea is the stored-program concept: both instructions and data are stored in the same memory and transferred over a single shared bus.
| Component | Role |
|---|---|
| Central Processing Unit (CPU) | Fetches, decodes and executes instructions |
| Main Memory (RAM) | Stores both program instructions and data in a single address space |
| System Bus | Connects the CPU to memory and I/O — comprises the address bus, data bus and control bus |
| Input/Output (I/O) | Peripheral devices connected through I/O controllers |
Because instructions and data share a single bus, the CPU cannot fetch an instruction and read or write data at the same time. The bus becomes a bottleneck — the processor may sit idle while waiting for a data transfer to complete.
Exam Tip: When describing the Von Neumann bottleneck, state clearly that the limitation arises because instructions and data share a single bus, not just because they share the same memory. Examiners want both points.
The Harvard architecture uses physically separate memories and buses for instructions and data.
| Component | Role |
|---|---|
| Processor (CPU) | Fetches, decodes and executes instructions |
| Instruction Memory | Dedicated memory for storing program instructions |
| Data Memory | Dedicated memory for storing data |
| Instruction Bus | Dedicated bus between CPU and instruction memory |
| Data Bus | Dedicated bus between CPU and data memory |
Harvard architecture is commonly found in:
Most modern desktop and laptop CPUs use a Modified Harvard architecture. At the main-memory level, instructions and data share a single RAM (Von Neumann style). However, inside the CPU there are separate Level 1 (L1) caches for instructions and data (Harvard style).
CPU
+--------------------+
| +------+ +------+ |
| | L1-I | | L1-D | | <-- Separate caches (Harvard-style)
| +--+---+ +--+---+ |
| +---+---+ |
| L2 Cache |
+--------+-----------+
|
Unified Main Memory <-- Single shared memory (Von Neumann-style)
This hybrid approach gives the speed advantage of Harvard (simultaneous instruction and data access at the cache level) and the flexibility of Von Neumann (a single main memory for programs and data).
| Feature | Von Neumann | Harvard | Modified Harvard |
|---|---|---|---|
| Memory | Shared for instructions and data | Separate memories | Shared main memory, split caches |
| Buses | Single shared bus | Separate instruction and data buses | Shared main bus, split at cache level |
| Bottleneck | Yes | No | Reduced (mitigated by caches) |
| Cost / complexity | Lower | Higher | Moderate |
| Typical use | General-purpose PCs (historically) | DSPs, microcontrollers | Modern desktop/laptop CPUs |
The processor contains several special-purpose registers that play specific roles during instruction processing.
| Register | Full Name | Purpose |
|---|---|---|
| PC | Program Counter | Holds the address of the next instruction to be fetched |
| MAR | Memory Address Register | Holds the address of the memory location about to be read from or written to |
| MDR | Memory Data Register | Holds the data that has just been read from memory, or the data about to be written to memory |
| CIR | Current Instruction Register | Holds the instruction currently being decoded and executed |
| ACC | Accumulator | A general-purpose register that holds the result of ALU operations |
PC ----> MAR ----> Address Bus ----> Memory
|
MDR <----> Data Bus <------------------->|
|
CIR <---- MDR
|
Control Unit ----> Control Bus ----> Memory / I/O
A bus is a set of parallel wires that carries data, addresses or control signals between components.
| Property | Detail |
|---|---|
| Direction | Unidirectional — from CPU to memory/I/O |
| Width | Determines the maximum addressable memory. A 32-bit address bus can address 2^32 = 4,294,967,296 locations (4 GB) |
| Purpose | Carries the address of the memory location or I/O port the CPU wants to access |
| Property | Detail |
|---|---|
| Direction | Bidirectional — data travels both from CPU to memory and from memory to CPU |
| Width | Determines how many bits can be transferred in a single operation. Common widths: 8, 16, 32, 64 bits |
| Purpose | Carries the actual data or instructions being transferred |
| Property | Detail |
|---|---|
| Direction | Bidirectional — some signals go from CPU to devices, others from devices to CPU |
| Key signals | Memory Read, Memory Write, I/O Read, I/O Write, Interrupt Request, Bus Request, Bus Grant, Clock |
| Purpose | Coordinates and controls the activities of all components connected to the bus |
Exam Tip: A common exam question asks you to explain the effect of increasing the width of the address bus vs the data bus. Increasing the address bus width allows the CPU to address more memory locations. Increasing the data bus width allows the CPU to transfer more data per operation, improving throughput. State both effects precisely.
Question: A computer has a 24-bit address bus and a 16-bit data bus. Calculate the maximum addressable memory and the amount of data that can be transferred in one operation.
Answer:
| Term | Definition |
|---|---|
| Stored-program concept | The idea that both instructions and data are stored in the same memory |
| Von Neumann bottleneck | The performance limitation caused by instructions and data sharing a single bus |
| Register | A small, fast storage location inside the CPU |
| Bus | A set of parallel wires connecting components for data, address or control signal transfer |
| Word size | The number of bits the CPU can process in a single operation, often matching the data bus width |