Pipelining

Pipelining is a technique that allows multiple instructions to be in different stages of execution simultaneously, significantly increasing the throughput of a processor. It is one of the most important A-Level topics in computer architecture.

---

The Concept

Without pipelining, the processor completes one full FDE cycle before starting the next:

Instruction 1:  [Fetch] [Decode] [Execute]
Instruction 2:                              [Fetch] [Decode] [Execute]
Instruction 3:                                                         [Fetch] [Decode] [Execute]

With pipelining, the stages overlap:

Clock cycle:     1       2        3        4        5
Instruction 1:  [Fetch] [Decode] [Execute]
Instruction 2:          [Fetch]  [Decode]  [Execute]
Instruction 3:                   [Fetch]   [Decode]  [Execute]

After the pipeline is full (cycle 3 onwards), one instruction completes every clock cycle, even though each individual instruction still takes three cycles.

---

How Pipelining Improves Throughput

Without Pipelining	With Pipelining (3-stage)
3 instructions in 9 cycles	3 instructions in 5 cycles
Throughput: 1 instruction every 3 cycles	Throughput: 1 instruction every cycle (once the pipeline is full)

For an n-stage pipeline executing k instructions:

• Without pipelining: n x k cycles
• With pipelining: n + (k - 1) cycles