Pipelining

Pipelining is a technique that allows multiple instructions to be in different stages of execution simultaneously, significantly increasing the throughput of a processor. It is one of the most important A-Level topics in computer architecture.

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The Concept

Without pipelining, the processor completes one full FDE cycle before starting the next:

Instruction 1:  [Fetch] [Decode] [Execute]
Instruction 2:                              [Fetch] [Decode] [Execute]
Instruction 3:                                                         [Fetch] [Decode] [Execute]

With pipelining, the stages overlap:

Clock cycle:     1       2        3        4        5
Instruction 1:  [Fetch] [Decode] [Execute]
Instruction 2:          [Fetch]  [Decode]  [Execute]
Instruction 3:                   [Fetch]   [Decode]  [Execute]

After the pipeline is full (cycle 3 onwards), one instruction completes every clock cycle, even though each individual instruction still takes three cycles.

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How Pipelining Improves Throughput

Without Pipelining	With Pipelining (3-stage)
3 instructions in 9 cycles	3 instructions in 5 cycles
Throughput: 1 instruction every 3 cycles	Throughput: 1 instruction every cycle (once the pipeline is full)

For an n-stage pipeline executing k instructions:

• Without pipelining: n x k cycles
• With pipelining: n + (k - 1) cycles

The deeper the pipeline (more stages), the greater the potential speedup — but also the greater the penalty when things go wrong.

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Modern Pipeline Stages

Real processors have many more than three stages. A typical modern pipeline might include:

1. Instruction Fetch (IF) — fetch the instruction from memory/cache.
2. Instruction Decode (ID) — decode the opcode, read registers.
3. Operand Fetch (OF) — fetch operands from registers or memory.
4. Execute (EX) — perform the ALU operation.
5. Memory Access (MEM) — read from or write to memory (for load/store instructions).
6. Write Back (WB) — write the result back to a register.

Some processors (e.g. Intel Pentium 4 NetBurst) had pipelines of 20 or even 31 stages.

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Pipeline Hazards

Pipelining does not always run smoothly. Hazards are situations that prevent the next instruction from executing in the next clock cycle, causing stalls (bubbles) in the pipeline.

1. Data Hazards

A data hazard occurs when an instruction depends on the result of a previous instruction that has not yet completed.

ADD R1, R2, R3    ; R1 = R2 + R3
SUB R4, R1, R5    ; R4 = R1 - R5  ← needs the new value of R1, which may not be written back yet