The Processor: Registers, Buses, and the FDE Cycle

At A-Level you must go beyond a surface-level understanding of the CPU. This lesson covers the internal architecture of a typical processor — its key registers, the bus system, and the detailed steps of the Fetch-Decode-Execute (FDE) cycle.

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Internal Structure of the CPU

A simplified block diagram of a processor includes:

┌─────────────────────────────────────────────────┐
│                    CPU                           │
│                                                  │
│  ┌────────┐   ┌────────┐   ┌────────────────┐   │
│  │  ALU   │   │  CU    │   │   Registers    │   │
│  └────────┘   └────────┘   │  PC, MAR, MDR, │   │
│                             │  CIR, ACC, IX  │   │
│                             └────────────────┘   │
└──────────────────┬──────────────────────────────┘
                   │  System Bus (Address + Data + Control)
                   ▼
            ┌────────────┐
            │ Main Memory│
            └────────────┘

The Arithmetic Logic Unit (ALU)

The ALU performs:

• Arithmetic operations — addition, subtraction, multiplication, division.
• Logical operations — AND, OR, NOT, XOR.
• Comparison operations — equal, greater than, less than (setting status flags).
• Shift operations — logical and arithmetic shifts.

The Control Unit (CU)

The CU coordinates the operation of the processor by:

• Directing the flow of data between the CPU and other devices.
• Decoding instructions fetched from memory.
• Generating control signals (timing pulses) sent along the control bus to synchronise operations.
• Managing the FDE cycle.

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Key Registers

Register	Full Name	Purpose
PC	Program Counter	Holds the address of the next instruction to be fetched
MAR	Memory Address Register	Holds the address of the memory location about to be read from or written to
MDR	Memory Data Register (also called MBR — Memory Buffer Register)	Holds the data that has just been read from memory or the data about to be written to memory
CIR	Current Instruction Register	Holds the instruction currently being decoded and executed
ACC	Accumulator	A general-purpose register that holds the result of ALU operations
IX	Index Register	Holds a value that is added to an address in indexed addressing mode
SR / Flags	Status Register	Contains individual flag bits (e.g. carry, zero, overflow, negative) set by ALU operations

Exam Tip: You must name registers precisely. "MAR" is not the same as "MDR". A common error is to mix up which register holds the address (MAR) and which holds the data (MDR). Remember: MAR = Address, MDR = Data.

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The System Bus

The system bus is composed of three separate buses:

Bus	Direction	Width (typical)	Purpose
Address bus	Unidirectional (CPU → memory)	32 or 64 lines	Carries the address of the memory location being accessed
Data bus	Bidirectional	8, 16, 32 or 64 lines	Carries data between CPU and memory / I/O
Control bus	Bidirectional	Varies	Carries control signals (read, write, clock, interrupt, bus request / bus grant)

Key Points About Bus Width

• The address bus width determines the maximum addressable memory. A 32-bit address bus can address 2^32 = 4 GB of memory.
• The data bus width determines how much data can be transferred in a single operation. A wider data bus means more data per transfer — higher throughput.
• Increasing either bus width improves performance but increases hardware cost and complexity.