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For decades, processor design has been pulled between two competing philosophies. One says: make instructions powerful — give the programmer a single instruction that can load from memory, do arithmetic and store the result, so programs are short and the hardware does the heavy lifting. This is Complex Instruction Set Computing (CISC). The other says: make instructions simple and uniform — give the processor a small set of single-cycle instructions that are trivial to decode and pipeline, and let the compiler assemble them into complex behaviour. This is Reduced Instruction Set Computing (RISC).
This is not an abstract argument. The CISC philosophy gave us the x86 chips in most desktops and servers; the RISC philosophy gave us the ARM chips in virtually every smartphone, tablet and Raspberry Pi. At A-Level you must be able to characterise each approach precisely, compare them across a defined set of criteria, explain why RISC pipelines more easily and uses less power, and — crucially for top marks — explain how modern processors have converged so that the distinction is now blurred.
This lesson maps to the AQA A-Level Computer Science (7517) specification, §4.7.3 Structure and role of the processor and its components:
It links directly to pipelining (the next lesson) and to the FDE cycle of §4.7.3, since the ease of pipelining is rooted in how instructions are fetched and decoded.
A CISC processor offers a large instruction set with many specialised instructions, some of which perform complex multi-step operations in a single instruction.
| Feature | Detail |
|---|---|
| Number of instructions | Large — hundreds of distinct opcodes |
| Instruction complexity | Some instructions do multi-step work (one instruction may load from memory, compute, and store) |
| Instruction length | Variable — different instructions occupy different numbers of bytes |
| Cycles per instruction | Variable — complex instructions take many clock cycles |
| Addressing modes | Many (often 10 or more) |
| Registers | Fewer general-purpose registers |
| Code density | High — fewer instructions per program, so smaller code |
| Hardware / control | Complex decode logic; instructions implemented in microcode |
The Intel x86 architecture (most PCs and servers) is the classic CISC design. A single x86 instruction such as REP MOVSB can copy an entire block of memory — work that would take a whole loop of simple instructions on a RISC processor. Variable-length encoding means one instruction might be one byte and another fifteen bytes.
A RISC processor offers a small, highly regular instruction set. Each instruction does one simple thing and (ideally) completes in a single clock cycle. Memory is touched only by dedicated load and store instructions (the load–store architecture); all arithmetic happens between registers.
| Feature | Detail |
|---|---|
| Number of instructions | Small — typically fewer than 100 core instructions |
| Instruction complexity | Each instruction performs one simple operation (load, add and store are separate) |
| Instruction length | Fixed — every instruction is the same width (e.g. 32 bits) |
| Cycles per instruction | Typically one (close to one with pipelining) |
| Addressing modes | Few (typically 3–5) |
| Registers | Many general-purpose registers (often 32 or more) |
| Code density | Lower — more instructions per program |
| Hardware / control | Simpler hardwired control, no microcode; spare transistors go to registers and cache |
ARM processors (smartphones, tablets, Raspberry Pi, and increasingly laptops/servers) follow the RISC philosophy. Each classic ARM instruction is 32 bits wide and most execute in a single cycle, which is part of why ARM chips achieve such good performance-per-watt.
The clearest way to feel the difference between the two philosophies is to express the same task both ways. Suppose we want to add the value in memory location X to the value in memory location Y and store the result back in Y (i.e. Y = Y + X).
On an idealised CISC processor, a single memory-to-memory ADD instruction can do the whole job, because CISC instructions are allowed to operate directly on memory operands:
ADD Y, X # one instruction: memory[Y] <- memory[Y] + memory[X]
On a RISC processor, which uses a strict load–store model where arithmetic happens only between registers, the same task requires several simple instructions:
LDR R1, X # load memory[X] into register R1
LDR R2, Y # load memory[Y] into register R2
ADD R2, R2, R1 # R2 <- R2 + R1 (register-to-register only)
STR R2, Y # store R2 back into memory[Y]
The CISC version is one instruction (higher code density, smaller program); the RISC version is four instructions (lower code density, larger program). But notice the flip side: every one of the four RISC instructions is short, fixed-length and does exactly one simple thing, so each takes a single, predictable cycle and the four pipeline beautifully. The single CISC instruction hides a multi-step memory-read / add / memory-write sequence that may take several cycles and is harder to overlap with its neighbours. This single example captures the entire trade-off: CISC trades cycles and pipelining ease for code density; RISC trades code size for simple, fast, pipeline-friendly instructions.
| Metric | CISC version | RISC version |
|---|---|---|
| Instructions | 1 | 4 |
| Program size | Smaller (denser) | Larger |
| Cycles per instruction | Many (one complex instruction) | One each (four simple instructions) |
| Pipelining | Harder | Easy |
| Memory operands in arithmetic | Allowed | Not allowed (load–store only) |
A defining internal difference between the two philosophies is how the control unit turns an instruction into control signals.
This is why a RISC chip can devote more of its transistor budget to registers and cache (which directly speed up real programs) while a CISC chip spends a chunk of its budget on microcode and complex decoders.
| Criterion | CISC | RISC |
|---|---|---|
| Instruction set size | Large | Small |
| Instruction length | Variable | Fixed |
| Clock cycles per instruction | Many (varies) | One (ideally) |
| Addressing modes | Many | Few |
| General-purpose registers | Fewer | Many |
| Control implementation | Microcode | Hardwired |
| Memory access | Most instructions can touch memory | Only load / store touch memory |
| Pipelining | Harder (variable length) | Easier (fixed length) |
| Code density | Higher (fewer instructions) | Lower (more instructions) |
| Compiler complexity | Lower (hardware handles complexity) | Higher (compiler must optimise) |
| Power consumption | Generally higher | Generally lower |
| Typical use | Desktop PCs, servers | Mobile, embedded, IoT (and now servers/laptops) |
This is the single most important consequence. Pipelining overlaps the fetch/decode/execute stages of consecutive instructions to raise throughput. Fixed-length RISC instructions make this easy: the processor always knows where the next instruction begins, so it can fetch instruction n+1 while instruction n is still being decoded.
flowchart LR
subgraph RISC["RISC: fixed-length — next start is known immediately"]
R1["instr n<br/>(4 bytes)"] --> R2["instr n+1<br/>(4 bytes)"] --> R3["instr n+2<br/>(4 bytes)"]
end
subgraph CISC["CISC: variable-length — must decode n to find n+1"]
C1["instr n<br/>(? bytes)"] --> C2["instr n+1<br/>(? bytes)"]
end
With variable-length CISC instructions, the processor cannot know where the next instruction starts until it has at least partly decoded the current one — a serious obstacle to deep pipelines.
There is a second, related advantage. Because RISC instructions each do one simple thing in one cycle, they divide naturally into uniform pipeline stages of similar duration, so the pipeline flows smoothly with few stalls. CISC instructions, by contrast, take different numbers of cycles — one instruction might complete in two cycles and the next in twelve — so the pipeline stages are uneven and the hardware must cope with instructions of wildly different durations occupying it at once. This irregularity causes structural complications and stalls that the regular RISC stream avoids. It is precisely to recover this regularity that modern x86 chips crack each variable-length CISC instruction into a stream of uniform, fixed-length micro-ops before pipelining them — effectively converting the CISC front end into a RISC-style back end.
RISC processors generally consume less power because:
The complexity does not vanish in RISC — it moves to the compiler. The compiler must break complex operations into sequences of simple instructions, allocate the many registers efficiently, and schedule instructions to avoid pipeline stalls. In CISC, the hardware (microcode) shoulders much of this, so the compiler's job is comparatively easier.
CISC's powerful instructions give higher code density — programs are smaller, which mattered greatly when memory was scarce and expensive. RISC programs need more instructions, so they are larger, but ample modern memory and instruction caches make this far less of a concern than it once was.
There is a neat way to see why the "fewer instructions" of CISC does not automatically mean "faster". The time a program takes can be written as:
Time=instructions×instructioncycles×cycleseconds
So the two philosophies attack different terms of the same equation. Which wins depends on the workload — there is no universal answer, which is exactly why examiners reward a balanced, scenario-specific evaluation rather than a blanket "RISC is faster". This equation also explains the convergence below: modern x86 chips keep CISC's low instruction count and achieve a near-RISC cycles-per-instruction by decoding to micro-ops.
Understanding why the debate arose helps you reason about it:
For the exam you need the principles and trade-offs, but knowing the history makes it obvious why the once-sharp distinction is now mostly an interface decision rather than a fundamental performance divide.
Top-band answers recognise that the clean CISC/RISC divide has largely dissolved:
The practical upshot is that the external instruction set (CISC or RISC) is now largely an interface/compatibility decision, while the internal microarchitecture of high-performance chips of both kinds looks broadly similar.
Exam Tip: A common 6-mark comparison asks you to discuss CISC vs RISC. Structure your answer around a fixed set of criteria — instruction-set size, instruction length, cycles per instruction, registers, pipelining ease, power, compiler complexity — and name concrete examples (x86 = CISC, ARM = RISC). Reserve a sentence for convergence (x86 decoding to micro-ops) to push into the top band.
It helps to anchor the theory to where each philosophy actually lives:
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