Unsigned and Signed Binary Arithmetic

A processor's arithmetic logic unit can only add and shift binary patterns — yet it must somehow handle negative numbers, subtraction and the limits imposed by a fixed register width. This lesson develops binary arithmetic rigorously: unsigned representation and addition (with carries), the two competing ways to represent negatives (sign-and-magnitude and two's complement), subtraction performed as addition using two's complement, how to detect overflow, and the exact range of values an $n$n-bit register can hold. Every claim is backed by a fully worked example, because in the exam you must show the arithmetic, not merely state the answer.

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Spec Mapping

This lesson covers the binary-arithmetic strand of the AQA A-Level Computer Science (7517) Fundamentals of data representation area:

• Unsigned binary — representing non-negative integers and the range available with $n$n bits.
• Unsigned binary arithmetic — addition of binary numbers including carry propagation.
• Signed binary using sign-and-magnitude — and its drawbacks (two zeros; addition does not "just work").
• Signed binary using two's complement — representation, negation, subtraction via addition, range, and overflow detection.

Two's complement is the representation real processors use for signed integers, so this material connects directly to the arithmetic logic unit and to integer data types in programming.

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Unsigned Binary

An unsigned $n$n-bit number uses every bit for magnitude — there is no sign. The value is the familiar weighted sum:

$N = \sum_{i=0}^{n-1} b_i \times 2^{\,i}$N=∑i=0n−1​bi​×2i

With $n$n bits there are $2^n$2n patterns representing the integers $0$0 to $2^n - 1$2n−1 inclusive:

$\text{unsigned range} = 0 \ \text{to}\ 2^{n}-1, \qquad \text{number of values} = 2^{n}$unsigned range=0 to 2n−1,number of values=2n

For an 8-bit byte that is $0$0 to $255$255; for 16 bits, $0$0 to $65{,}535$65,535.

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Unsigned Binary Addition

Binary addition uses exactly the column-by-column carry method you know from denary, but with only four single-bit rules:

A	B	Carry-in	Sum bit	Carry-out
0	0	0	0	0
0	1	0	1	0
1	0	0	1	0
1	1	0	0	1
1	1	1	1	1

The phrase to memorise: $1 + 1 = 10_2$1+1=102​ (zero carry one), and $1 + 1 + 1 = 11_2$1+1+1=112​ (one carry one).

Worked example: 8-bit addition with carries

Add $\texttt{01011110}_2$010111102​ ($94$94) and $\texttt{00101101}_2$001011012​ ($45$45). Working from the right, tracking carries:

Column	$2^7$27	$2^6$26	$2^5$25	$2^4$24	$2^3$23	$2^2$22	$2^1$21	$2^0$20
Carry	0	1	1	1	1	1	1	—
A	0	1	0	1	1	1	1	0
B	0	0	1	0	1	1	0	1
Sum	1	0	0	0	1	0	1	1

The result is $\texttt{10001011}_2$100010112​. Check: $128 + 8 + 2 + 1 = 139 = 94 + 45$128+8+2+1=139=94+45. Correct.

Exam Tip: Lay carries out in a clearly labelled row above the operands. Most marks for binary addition are for evidence of correct carry handling, so a tidy, explicit carry row protects you even if the final reading slips.

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Signed Binary 1: Sign-and-Magnitude

The simplest scheme to represent negatives reserves the most significant bit as a sign bit: 0 means positive, 1 means negative. The remaining $n-1$n−1 bits hold the magnitude in plain binary.

For 8 bits:

• $+45$+45 is $\texttt{0}\,\texttt{0101101}$00101101 → 00101101
• $-45$−45 is $\texttt{1}\,\texttt{0101101}$10101101 → 10101101 (same magnitude bits, sign bit flipped)

The range is symmetric: $-(2^{n-1}-1)$−(2n−1−1) to $+(2^{n-1}-1)$+(2n−1−1), which for 8 bits is $-127$−127 to $+127$+127.

Two serious drawbacks

1. There are two zeros. $\texttt{00000000}$00000000 is $+0$+0 and $\texttt{10000000}$10000000 is $-0$−0. Two bit patterns for one value wastes a code and complicates equality testing.
2. Ordinary binary addition does not work. Adding the patterns for $+5$+5 and $-5$−5 gives $\texttt{00000101} + \texttt{10000101} = \texttt{10001010}$00000101+10000101=10001010, which reads as $-10$−10, not $0$0. The hardware would need separate, more complex circuitry to decide whether to add or subtract magnitudes and how to set the sign.

These flaws are exactly why real processors do not use sign-and-magnitude for integer arithmetic.

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Signed Binary 2: Two's Complement

Two's complement is the representation that fixes both problems: it has a single zero, and the same adder circuit that does unsigned addition also gives correct signed results. It achieves this by giving the most significant bit a negative place value.

For an 8-bit two's complement number the columns are:

$\begin{array}{cccccccc} -2^7 & 2^6 & 2^5 & 2^4 & 2^3 & 2^2 & 2^1 & 2^0 \\ -128 & 64 & 32 & 16 & 8 & 4 & 2 & 1 \end{array}$−27−128​2664​2532​2416​238​224​212​201​

Only the MSB is negative; all other columns are positive as usual.

Reading a two's complement number

Evaluate $\texttt{11010110}_2$110101102​ in 8-bit two's complement:

$-128 + 64 + 16 + 4 + 2 = \mathbf{-42}$−128+64+16+4+2=−42

Because the MSB is 1, the value is negative — the MSB still acts as a sign indicator, but now it carries a weight rather than just a flag.

The range of two's complement

With the $-2^{n-1}$−2n−1 column, the most negative value is $-2^{n-1}$−2n−1 (MSB alone) and the most positive is $2^{n-1}-1$2n−1−1 (all lower bits set):

$\text{two's complement range} = -2^{\,n-1} \ \text{to}\ 2^{\,n-1}-1$two’s complement range=−2n−1 to 2n−1−1

For 8 bits this is $-128$−128 to $+127$+127. Note the asymmetry: there is one more negative value than positive, and crucially only one zero ($\texttt{00000000}$00000000).

Ranges at common bit widths

Examiners often ask for the range at widths other than 8 bits. Apply $-2^{n-1}$−2n−1 to $2^{n-1}-1$2n−1−1 for signed, and $0$0 to $2^n - 1$2n−1 for unsigned:

Bits $n$n	Unsigned range	Two's complement range
4	0 to 15	−8 to +7
8	0 to 255	−128 to +127
16	0 to 65 535	−32 768 to +32 767
32	0 to ≈4.29 billion	≈ −2.15 billion to +2.15 billion

Two facts the mark scheme rewards: (i) the unsigned maximum is always one less than the number of patterns ($2^n - 1$2n−1, because one pattern is zero); and (ii) the signed range is almost symmetric but has one extra negative value, so the most negative number has no positive counterpart of the same magnitude in that width. For instance, in 8 bits you can store $-128$−128 but not $+128$+128. Attempting to negate $-128$−128 ($\texttt{10000000}$10000000) by invert-and-add-one gives $\texttt{01111111} + 1 = \texttt{10000000}$01111111+1=10000000 — back to $-128$−128 — a neat illustration that $+128$+128 is simply not representable and the operation overflows.

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Negating a Number in Two's Complement

To find the representation of $-x$−x from $+x$+x (or vice versa) there are two equivalent methods.

Method A — invert and add one

Flip every bit (the one's complement), then add 1. Find $-42$−42 from $+42 = \texttt{00101010}$+42=00101010:

Step	Bits
$+42$+42	0 0 1 0 1 0 1 0
Invert every bit	1 1 0 1 0 1 0 1
Add 1	1 1 0 1 0 1 1 0

So $-42 = \texttt{11010110}_2$−42=110101102​ — exactly the pattern we decoded earlier.

Method B — copy up to and including the first 1, then flip the rest

Working from the right, copy bits up to and including the first 1, then invert everything to its left. For $+42 = \texttt{00101010}$+42=00101010 the first 1 from the right is in the $2^1$21 column:

Original	0 0 1 0 1 0 1 0
Copy up to & incl. first 1 (the 10)	_ _ _ _ _ _ 1 0
Flip the rest	1 1 0 1 0 1 1 0

Same result, $\texttt{11010110}_2$110101102​. Method A is more reliable under pressure; Method B is faster once practised.

A neat consistency check: applying the negation twice must return the original number. Invert-and-add-one applied to $\texttt{11010110}$11010110 gives $\texttt{00101001} + 1 = \texttt{00101010} = +42$00101001+1=00101010=+42.

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Subtraction via Two's Complement

The headline benefit: to compute $A - B$A−B, negate $B$B and add. $A - B = A + (-B)$A−B=A+(−B). The processor needs only an adder and a bit-inverter, not a separate subtractor.

Worked example: 75 − 42

Both in 8-bit two's complement:

• $A = +75 = \texttt{01001011}$A=+75=01001011
• $B = +42 = \texttt{00101010}$B=+42=00101010, so $-B = \texttt{11010110}$−B=11010110 (computed above).

Now add $A + (-B)$A+(−B):

Column	$-2^7/2^7$−27/27	$2^6$26	$2^5$25	$2^4$24	$2^3$23	$2^2$22	$2^1$21	$2^0$20
Carry	1	1	0	0	0	0	1	—
$A$A	0	1	0	0	1	0	1	1
$-B$−B	1	1	0	1	0	1	1	0
Sum	(1)0	0	1	0	0	0	0	1

A carry of 1 is produced out of the MSB. In two's complement subtraction this final carry-out is simply discarded — we keep the 8-bit result $\texttt{00100001}_2$001000012​. Check: $32 + 1 = 33 = 75 - 42$32+1=33=75−42. Correct.

Worked example: 42 − 75 (a negative result)

• $A = +42 = \texttt{00101010}$A=+42=00101010
• $B = +75 = \texttt{01001011}$B=+75=01001011, so $-B =$−B= invert ($\texttt{10110100}$10110100) + 1 $= \texttt{10110101}$=10110101.

Add:

Column	$-2^7/2^7$−27/27	$2^6$26	$2^5$25	$2^4$24	$2^3$23	$2^2$22	$2^1$21	$2^0$20
Carry	0	0	1	1	1	0	0	—
$A$A	0	0	1	0	1	0	1	0
$-B$−B	1	0	1	1	0	1	0	1
Sum	1	1	0	1	1	1	1	1

Result $\texttt{11011111}_2$110111112​. There is no carry out of the MSB. Decoding: $-128 + 64 + 16 + 8 + 4 + 2 + 1 = -33$−128+64+16+8+4+2+1=−33. And indeed $42 - 75 = -33$42−75=−33. Correct — the answer comes out already in two's complement form with no special handling for the sign.

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Detecting Overflow

A fixed-width register can only hold values in its range. Overflow occurs when the true mathematical result falls outside $-2^{n-1} \ldots 2^{n-1}-1$−2n−1…2n−1−1, so the stored result is wrong.

The reliable rule for two's complement addition:

Overflow has occurred if and only if the two operands have the same sign but the result has the opposite sign. Adding two positives can only overflow to a (wrong) negative; adding two negatives can only overflow to a (wrong) positive. Adding a positive and a negative can never overflow.

An equivalent hardware rule: overflow occurs when the carry into the MSB differs from the carry out of the MSB.

Worked example: overflow on 100 + 50

In 8 bits, $100 + 50 = 150$100+50=150, but the maximum is $127$127 — so we expect overflow.

• $+100 = \texttt{01100100}$+100=01100100, $+50 = \texttt{00110010}$+50=00110010.

Column	$-2^7/2^7$−27/27	$2^6$26	$2^5$25	$2^4$24	$2^3$23	$2^2$22	$2^1$21	$2^0$20
Carry	0	1	1	0	0	0	0	—
A	0	1	1	0	0	1	0	0
B	0	0	1	1	0	0	1	0
Sum	1	0	0	1	0	1	1	0

The carry into the MSB is 1 but the carry out is 0 — they differ, so overflow is flagged. Confirming with the sign rule: both operands were positive (MSB 0) yet the result $\texttt{10010110}$10010110 has MSB 1, i.e. it decodes as $-128 + 16 + 4 + 2 = -106$−128+16+4+2=−106, which is nonsense for $100 + 50$100+50. The hardware would set the overflow flag in the status register.

Worked example: overflow on two negatives

Overflow is symmetric — adding two negatives can overflow to a wrong positive. Compute $-100 + (-50)$−100+(−50) in 8 bits, where the true answer $-150$−150 is below the minimum $-128$−128.

• $-100 = \texttt{10011100}$−100=10011100 (check: $-128 + 16 + 8 + 4 = -100$−128+16+8+4=−100); $-50 = \texttt{11001110}$−50=11001110 (check: $-128 + 64 + 8 + 4 + 2 = -50$−128+64+8+4+2=−50).

Column	$-2^7/2^7$−27/27	$2^6$26	$2^5$25	$2^4$24	$2^3$23	$2^2$22	$2^1$21	$2^0$20
Carry	0	1	1	1	1	1	1	—
A	1	0	0	1	1	1	0	0
B	1	1	0	0	1	1	1	0
Sum	(1)0	1	1	0	1	0	1	0

A carry of 1 leaves the MSB (discarded), and the carry into the MSB is 0 — carry-in (0) differs from carry-out (1), so overflow is flagged. By the sign rule, two negative operands have produced a result $\texttt{01101010}$01101010 with MSB 0 (positive: $+106$+106), which is impossible for $-150$−150. Overflow has occurred and the 8-bit result is invalid — exactly mirroring the two-positives case, which is why the single carry-in ≠ carry-out test catches both directions of overflow.

Why discarded carry ≠ overflow