Sequential Logic, Flip-Flops and Counters

Combinational logic, the subject of Lesson 4, is "memoryless" — the outputs depend only on the current inputs. Sequential logic, by contrast, has internal state: its outputs depend on the inputs and on what has happened previously. This single extension — adding memory — is what turns a static collection of gates into a dynamic system that can count, sequence, store data, and execute programs. Sequential logic is built by feeding outputs back to inputs through gate networks, creating a bistable element called a latch or flip-flop that can remain in either of two stable states indefinitely. Networks of flip-flops form registers (storing multi-bit values), counters (incrementing on each clock pulse), and shift registers (passing data along a chain). Every digital clock, every microprocessor program counter, every USB serial-data interface and every camera's image-sensor row scanner is built from these elements. This lesson develops the SR latch from cross-coupled NOR gates, the clocked D and JK flip-flops, asynchronous and synchronous counters, and the four shift-register topologies.

Spec mapping (AQA 7408 §3.13.4 — Digital signal processing, option E, continued): This lesson covers the bistable SR latch built from cross-coupled NOR (or NAND) gates with the set-reset state-machine behaviour; the D flip-flop (data, clocked) and JK flip-flop (the universal sequential element); the distinction between edge-triggered and level-sensitive operation; asynchronous (ripple) and synchronous binary counters including modulo-N designs; shift registers in their four configurations (SISO, SIPO, PISO, PIPO); and applications in digital clocks, frequency dividers, and serial-to-parallel data conversion. (Refer to the official AQA specification document for exact wording.)

Synoptic links: Sequential logic is built from the combinational gates of Lesson 4 — the cross-coupled NORs of an SR latch are still just NOR gates, plus feedback. The clocked D flip-flop is the basic memory cell of every CPU register and of every static RAM (SRAM) chip; it is also the storage element behind the digital-signal sampling discussed in Lesson 1 (each ADC sample must be latched into a register before the next can begin). Counters are also the workhorse behind every digital frequency divider — the carry output of a counter chain is a frequency that is the input clock divided by 2^N, exactly the divider used in PLL frequency synthesisers in modulation systems (Lesson 6).

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The Bistable — A Memory Cell Built from Gates

To create memory from a gate network, feed the output of a gate back to its input. The simplest such circuit uses two NOR (or NAND) gates cross-coupled:

S ──[NOR]──┬──── Q
           │ ↺
           │
   ┌───────┘
   │
R ──[NOR]──┬──── Q̄
           │ ↺
           │
   ┌───────┘
   │

(The cross-coupling: each gate's output feeds the other gate's second input.)

The SR Latch — Truth Table

S	R	Q (next)	Q̄ (next)	Description
0	0	Q (no change)	Q̄ (no change)	Hold
1	0	1	0	Set
0	1	0	1	Reset
1	1	forbidden	forbidden	Both inputs high invalid

The (S=1, R=1) combination is forbidden because both NOR outputs would try to be 0 simultaneously, which is inconsistent with the cross-coupled feedback. In practice the latch settles into whichever state the slightly faster gate reaches first — a non-deterministic outcome that engineers must avoid.

State Machine View

A state diagram captures the SR latch's behaviour:

graph LR
    A["Q=0<br/>(Reset)"] -->|S=1| B["Q=1<br/>(Set)"]
    B -->|R=1| A
    A -->|S=0,R=0| A
    B -->|S=0,R=0| B
    A -->|S=1,R=1| C["Forbidden"]
    B -->|S=1,R=1| C

    style A fill:#3498db,color:#fff
    style B fill:#27ae60,color:#fff
    style C fill:#e74c3c,color:#fff

The latch has two stable states (Q=0 and Q=1), transitions controlled by S and R, and one forbidden combination.

Worked Example — Switch Debouncing

Question: A push-button switch produces electrical contact "bounce" — a few milliseconds of repeated open–close transitions when the contact closes. Explain how an SR latch eliminates the bounce.

Solution: Wire the switch as a single-pole double-throw (SPDT) configuration with one common pole and two contacts labelled S and R. When the switch is in the "set" position, S = 1 (latch sets Q=1); on contact bounce, S returns briefly to 0 but Q stays at 1 (the hold state). Only when the switch is moved to the other contact does R go to 1 and Q reset to 0. Any momentary contact bounce after that first set is invisible — the latch is already in the desired state and ignores subsequent bounces. The latch behaves as a "first transition wins" filter, perfectly suited to debouncing.

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Clocked Flip-Flops

The asynchronous SR latch responds to inputs immediately. For predictable digital design we usually want changes to happen only at specific moments — at the rising or falling edge of a clock signal. A flip-flop is a latch with an added clock input, and changes state only when the clock transitions.

The D Flip-Flop (Data / Delay)

The D flip-flop has a single data input D, a clock input CLK, and outputs Q and Q̄. The behaviour is the simplest of all sequential elements: on each rising edge of CLK, the value at D is copied to Q. Between clock edges, Q retains its previous value.

CLK	D	Q (next)
↑	0	0
↑	1	1
0 or 1 (static)	any	Q (no change)

The D flip-flop is the standard memory element in synchronous digital systems. Strings of D flip-flops sharing a common clock form registers of any width; a 32-bit register is 32 D flip-flops in parallel.

The JK Flip-Flop

The JK flip-flop is the most general edge-triggered flip-flop. It has two inputs J (set) and K (reset), plus a clock. The truth table on each rising clock edge:

J	K	Q (next)	Action
0	0	Q (no change)	Hold
1	0	1	Set
0	1	0	Reset
1	1	Q̄ (toggle)	Toggle

The (J=1, K=1) case toggles the output — Q flips on every clock edge. This is what makes the JK flip-flop universal for sequential design: with J=K=1 it forms a divide-by-2 frequency divider; with J=D, K=D̄ it behaves like a D flip-flop; with J=S, K=R it behaves like a clocked SR latch.

Edge-Triggered vs Level-Sensitive

A level-sensitive latch responds whenever the clock is in the active level (e.g. while CLK=1). This makes data races possible: if the data D is changing while the clock is high, the latch may output an indeterminate value.

An edge-triggered flip-flop responds only at the instant of the clock transition (the rising edge or the falling edge, depending on design). The data is sampled at that single instant and held for the entire clock period; whatever happens to D between edges is ignored.

Modern synchronous digital systems are universally edge-triggered for predictability and ease of timing analysis.

Worked Example — Frequency Divider

Question: A 1 MHz clock is fed into the clock input of a JK flip-flop wired with J=K=1. (a) State the frequency at the Q output. (b) Cascade four such flip-flops, each driven by the previous Q. State the output frequency.

Solution:

(a) With J=K=1, the flip-flop toggles on every rising clock edge. Q completes one full cycle (low → high → low) every two clock cycles. The output frequency is 1 MHz / 2 = 500 kHz.

(b) Each stage divides by 2. Four stages divide by 2⁴ = 16. Output frequency = 1 MHz / 16 = 62.5 kHz.

This is the basis of every digital clock circuit. A 32.768 kHz quartz crystal is divided down by 15 stages (factor 2¹⁵ = 32 768) to produce a 1 Hz tick.

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Asynchronous Counters (Ripple Counters)

The cascade in the previous example is an asynchronous binary counter (also called a ripple counter). Each flip-flop's clock comes from the previous flip-flop's Q output. The output bits form a binary number that counts up on every rising edge of the input clock.

graph LR
    CLK[CLK input] --> FF0["FF0<br/>J=K=1"]
    FF0 -->|Q0| FF1["FF1<br/>J=K=1"]
    FF1 -->|Q1| FF2["FF2<br/>J=K=1"]
    FF2 -->|Q2| FF3["FF3<br/>J=K=1"]

    style CLK fill:#3498db,color:#fff
    style FF3 fill:#27ae60,color:#fff

After 16 clock pulses the four-bit output Q3Q2Q1Q0 has cycled through every binary value from 0000 to 1111 and returned to 0000.

Modulo-N Counters

A binary counter naturally cycles through 2^N states. To cycle through some other number — say, 10 for a decimal display — we add reset logic. A modulo-10 counter cycles through 0 to 9 and resets to 0 on the next pulse:

• Detect the state "10" (binary 1010) using an AND gate on Q3 and Q1.
• Feed this signal back to the asynchronous CLEAR input of all four flip-flops.
• The counter momentarily reaches 1010, then is cleared back to 0000.

The brief moment at state 1010 is a glitch usually too short to matter, but careful designers use synchronous clear logic instead.

Disadvantages of Ripple Counters

The ripple structure has one critical weakness: the carry propagates sequentially. Each flip-flop's output must finish transitioning before the next can begin. After N stages, the total delay is N × t_pd (propagation delay per stage). For a 16-bit ripple counter at the maximum clock rate the output bits arrive in succession — Q0 first, Q15 last — and any logic reading the counter sees momentarily inconsistent values during the transition.

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Synchronous Counters

A synchronous counter drives every flip-flop's clock from the same input signal, so all transitions happen at the same instant. The logic that decides whether each flip-flop should toggle on a given edge is combinational logic on the existing counter state.

For a synchronous up-counter: flip-flop i toggles on a clock edge if all of Q0, Q1, …, Q_{i-1} are currently 1. This is achieved by feeding the AND of all lower bits into the JK inputs of stage i.

Worked Example — Designing a Mod-10 Counter

Question: Design a synchronous modulo-10 counter using JK flip-flops.

Solution: We need four flip-flops (since 10 > 2³ = 8 but 10 ≤ 2⁴ = 16). The counter cycles through 0000 (0), 0001 (1), ..., 1001 (9), back to 0000 (0).

The transitions:

• Q0 toggles every clock pulse → J0 = K0 = 1.
• Q1 toggles when Q0 = 1 and not at state 1001 → 0000 (i.e. when Q3 = 0). The standard solution: J1 = K1 = Q0 · Q̄3.
• Q2 toggles when Q1 · Q0 = 1 → J2 = K2 = Q1 · Q0.
• Q3 toggles when (Q2 · Q1 · Q0) is true (the count is at 7 going to 8) or when state = 1001 is reached (to reset Q3 from 1 to 0). The standard solution: J3 = Q2 · Q1 · Q0; K3 = Q0 (Q3 resets when state 1001 advances).

The result is a synchronous mod-10 counter cycling correctly through the ten decimal states with all outputs changing on the same clock edge.

Modulo-10 counters are the building block of decimal counter displays, digital wristwatches, and event-counter instruments. Cascaded mod-10 counters give a decimal frequency divider chain — divide by 10, then 10, then 10, etc.

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Shift Registers

A shift register is a chain of flip-flops in which each flip-flop's output feeds the next flip-flop's input. On each clock edge, every bit shifts one position to the right (or left, depending on wiring). A new bit is introduced at one end and the bit at the other end is lost (or fed back into the chain to form a circular shifter).

The Four Configurations

Shift registers are classified by how data is loaded in and read out:

• SISO (Serial In, Serial Out): data is shifted in one bit at a time at the input; one bit at a time appears at the output. Used as a delay line or a serial-data buffer.
• SIPO (Serial In, Parallel Out): data is shifted in serially; after N clock pulses the entire N-bit word is available in parallel from the N flip-flop outputs. Used in serial-to-parallel conversion at a UART receiver.
• PISO (Parallel In, Serial Out): a parallel word is loaded into the flip-flops via a load input; the data is then shifted out serially one bit per clock. Used at a UART transmitter.
• PIPO (Parallel In, Parallel Out): simply a parallel register — N bits loaded simultaneously, N bits read simultaneously. This is essentially an N-bit D-flip-flop array.

Application — Serial Communication