The Fetch-Decode-Execute Cycle

This lesson explains the fetch-decode-execute (FDE) cycle, which is the fundamental process by which a CPU processes every instruction in a program. This topic is essential for AQA and OCR GCSE Computer Science.

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Overview

The CPU does not process an entire program in one go. Instead, it works through instructions one at a time in a continuous loop called the fetch-decode-execute cycle. This cycle repeats billions of times per second in a modern computer.

The three stages are:

1. Fetch — retrieve the next instruction from memory.
2. Decode — interpret what the instruction means.
3. Execute — carry out the instruction.

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The Cycle as a Flowchart

graph TD
    A["Fetch: PC -> MAR -> read RAM -> MDR"] --> B["Increment PC"]
    B --> C["Decode: split into Opcode + Operand"]
    C --> D["Execute: ALU / Memory / Branch"]
    D --> A

Stage 1: Fetch

During the fetch stage, the CPU retrieves the next instruction from main memory (RAM). Here is what happens step by step:

1. The Program Counter (PC) holds the memory address of the next instruction.
2. The address in the PC is copied to the Memory Address Register (MAR).
3. The MAR sends this address along the address bus to main memory.
4. The Control Unit sends a read signal along the control bus.
5. The instruction stored at that memory address is sent along the data bus to the Memory Data Register (MDR).
6. The Program Counter is incremented (increased by 1) so it now points to the address of the next instruction.

Step	Action	Components Involved
1	PC holds address of next instruction	PC
2	Address copied from PC to MAR	PC, MAR
3	Address sent to memory via address bus	MAR, address bus
4	Read signal sent via control bus	CU, control bus
5	Instruction sent from memory to MDR via data bus	Memory, data bus, MDR
6	PC incremented by 1	PC

Exam Tip: Many students forget step 6 — the PC must be incremented during the fetch stage so that the next cycle fetches the correct instruction. Write this step explicitly in exam answers.

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Stage 2: Decode

During the decode stage, the CPU works out what the fetched instruction means:

1. The instruction is transferred from the MDR to the Control Unit (CU).
2. The CU uses an instruction decoder to split the instruction into two parts:
   • Opcode — this tells the CPU what operation to perform (e.g., ADD, STORE, LOAD, BRANCH).
   • Operand — this provides the data or the memory address of the data that the operation will use.
3. The CU determines which other components are needed and prepares control signals.

For example, the instruction ADD 7 has:

• Opcode: ADD
• Operand: 7 (add the value 7 to the accumulator)

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Stage 3: Execute

During the execute stage, the CPU carries out the instruction. What happens depends on the type of instruction:

• Arithmetic/logic instruction (e.g., ADD, SUBTRACT, COMPARE): The ALU performs the calculation and stores the result in the Accumulator (ACC).
• Data transfer instruction (e.g., LOAD, STORE): Data is moved between the CPU registers and main memory.
• Branch instruction (e.g., JUMP, BRANCH IF EQUAL): The Program Counter is changed to a new address, causing the CPU to start fetching instructions from a different part of the program.

Instruction Type	Example	What Happens
Arithmetic	ADD 5	ALU adds 5 to the accumulator
Logic	COMPARE 10	ALU compares accumulator with 10
Data transfer	LOAD 200	Data at address 200 is loaded into the accumulator
Branch	JUMP 50	PC is set to 50; next instruction fetched from address 50

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The Cycle Repeats

After the execute stage, the cycle starts again from the fetch stage. The PC (which was incremented in step 6 of the fetch stage, or changed by a branch instruction in the execute stage) now points to the next instruction.

This process continues indefinitely while the computer is running — billions of cycles per second in a modern processor.

      +--------+
      | FETCH  |  <--- PC provides address; instruction fetched from memory
      +--------+
          |
          v
      +--------+
      | DECODE |  <--- CU interprets the opcode and operand
      +--------+
          |
          v
      +---------+
      | EXECUTE |  <--- ALU, registers, or memory carry out the instruction
      +---------+
          |
          +-------> (back to FETCH)

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Worked Example

Suppose the following instructions are stored in memory:

Address	Instruction
100	LOAD 50
101	ADD 30
102	STORE 51

Cycle 1:

• Fetch: PC = 100. MAR = 100. Instruction "LOAD 50" fetched into MDR. PC becomes 101.
• Decode: CU decodes opcode LOAD and operand 50 (a memory address).
• Execute: Data at memory address 50 is loaded into the ACC.

Cycle 2:

• Fetch: PC = 101. MAR = 101. Instruction "ADD 30" fetched into MDR. PC becomes 102.
• Decode: CU decodes opcode ADD and operand 30 (a memory address).
• Execute: ALU adds the data at memory address 30 to the value in ACC. Result stored in ACC.

Cycle 3:

• Fetch: PC = 102. MAR = 102. Instruction "STORE 51" fetched into MDR. PC becomes 103.
• Decode: CU decodes opcode STORE and operand 51 (a memory address).
• Execute: The value in the ACC is written to memory address 51.

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Common Exam Questions

1. Describe the purpose of the fetch-decode-execute cycle. — It is the process by which the CPU fetches an instruction from memory, decodes what the instruction means, and then executes it. This cycle repeats for every instruction in a program.

2. Explain what happens to the Program Counter during the fetch stage. — The address in the PC is copied to the MAR, then the PC is incremented by 1 so it points to the next instruction.