Flip-Flops

Every circuit so far in this course has been combinational: its output is a pure function of its present inputs, with no memory of what came before. A flip-flop breaks that mould. It is the simplest sequential circuit — one whose output depends not only on the current inputs but also on its own previous state. That single capability, remembering one bit, is the foundation of everything that distinguishes a computer from a calculator: registers, counters, the contents of RAM, the program counter, the state of a finite-state machine. The OCR H446 specification requires you to know the SR, D-type and JK flip-flops — their behaviour, their clocked operation, and their uses — and, crucially, to articulate the dividing line between combinational and sequential logic.

The mechanism that gives a flip-flop memory is feedback: an output is wired back to an input, so the circuit can sustain a value indefinitely once set. This is exactly what combinational circuits lack — they have no loops, so they cannot "hold". Adding feedback creates two stable states (a bistable), and the various flip-flop types are different front-ends bolted onto that bistable core to control how and when it changes. The other half of the story is the clock: in any real system, flip-flops change state only at precise, synchronised instants dictated by a clock signal, so that the whole machine advances in lockstep. Memory plus a clock is what turns a heap of gates into a sequenced, stateful processor — which is why this lesson is the bridge from Boolean logic to computer architecture.

Every truth/state table below is a markdown table and every circuit a diagram — never ASCII art.

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Spec Mapping

This lesson covers the sequential-logic strand of OCR H446 section 1.4.3 (Boolean algebra and its application), linking forward to processor architecture in 1.1:

• The distinction between combinational and sequential logic, and the role of feedback in giving a circuit memory.
• The SR flip-flop: its state table, its cross-coupled NOR/NAND construction, and the problematic $S=R=1$S=R=1 input.
• Clocked and edge-triggered operation, including the meaning of rising/falling edges and why edge triggering is preferred.
• The D-type flip-flop (data latch / register cell) and the JK flip-flop (with its toggle state), and their typical uses.
• Applications: registers, counters and memory cells built from flip-flops.

It depends on logic gates (especially NOR/NAND) and the logic-circuits lesson, and it connects to clock-driven processor operation and the fetch–decode–execute cycle.

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Combinational vs Sequential Logic

Aspect	Combinational	Sequential
Output depends on	current inputs only	current inputs and stored state
Memory of the past?	none	yes (one or more bits)
Feedback loops?	no	yes — output fed back to input
Timing	responds whenever inputs change	typically changes only on a clock edge
Examples	gates, adders, multiplexers, decoders	flip-flops, registers, counters, RAM

The defining difference is state. A combinational adder given the same inputs always produces the same output, instantly (after propagation delay) and forgetfully. A sequential circuit given the same inputs may behave differently depending on what it currently stores — a JK flip-flop with $J=K=1$J=K=1 outputs 0 or 1 on the next edge depending entirely on its present value. That dependence on history is memory, and it is created by feedback.

Key Term: A flip-flop is a bistable sequential circuit storing one bit. It has two stable states (0 and 1) and holds whichever it is in until an input (and, when clocked, a clock edge) tells it to change.

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The SR Flip-Flop (Set–Reset)

The SR flip-flop is the simplest bistable. It has two inputs — S (Set) and R (Reset) — and two complementary outputs, Q and $\overline{Q}$Q​.

S	R	Q (next state)	Meaning
0	0	Q (unchanged)	Hold — outputs keep their current values
0	1	0	Reset — force Q to 0
1	0	1	Set — force Q to 1
1	1	invalid	Forbidden — see below

Cross-coupled NOR construction. The bistable is two NOR gates, each one's output feeding back into the other's input — the feedback that creates memory:

flowchart LR
    R((R)) --> NOR1{{"NOR"}}
    S((S)) --> NOR2{{"NOR"}}
    NOR1 -- "Q" --> Q["Q"]
    NOR2 -- "Q̄" --> NQ["Q̄"]
    NQ -- "feedback" --> NOR1
    Q -- "feedback" --> NOR2

Trace the hold state ($S=R=0$S=R=0): a NOR outputs 1 only when both inputs are 0. If Q is currently 1 then $\overline{Q}=0$Q​=0; feeding $\overline{Q}=0$Q​=0 and $R=0$R=0 into NOR1 keeps Q=1, and feeding $Q=1$Q=1 into NOR2 keeps $\overline{Q}=0$Q​=0. The loop sustains itself — the circuit remembers. Asserting $R=1$R=1 forces Q to 0; asserting $S=1$S=1 forces Q to 1.

Why $S=R=1$S=R=1 is forbidden. Setting both inputs to 1 drives both NOR outputs to 0, so $Q=\overline{Q}=0$Q=Q​=0 — the two outputs are no longer complements, violating the flip-flop's basic invariant. Worse, if both inputs then return to 0 simultaneously, the circuit cannot decide which stable state to fall into: the outcome depends on tiny timing differences (a race condition), so the final state is unpredictable. This is the headline weakness of the SR flip-flop, and the D and JK types are precisely the fixes for it.

An equivalent flip-flop can be built from two cross-coupled NAND gates, in which case the inputs are active-low ($\overline{S}$S, $\overline{R}$R) and the forbidden combination is $\overline{S}=\overline{R}=0$S=R=0 instead.

Worked sequence: watching the latch remember

The memory property is clearest when you apply a sequence of inputs and watch Q persist between them. Starting from $Q=0$Q=0 and applying the inputs in order:

Step	S	R	Q after	What happened
1	0	0	0	Hold — Q keeps its initial 0
2	1	0	1	Set — Q driven to 1
3	0	0	1	Hold — Q stays 1 even though S has gone
4	0	0	1	Still holding 1
5	0	1	0	Reset — Q driven to 0
6	0	0	0	Hold — Q stays 0

Step 3 is the whole point: after the Set pulse is removed (S back to 0), Q remains 1. A combinational OR gate fed the same inputs would immediately drop its output when S returned to 0; the latch does not, because the feedback loop sustains the value. This persistence-after-the-input-is-gone is exactly what "storing a bit" means, and it is impossible without feedback.

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How Feedback Creates Memory

It is worth drawing out the principle, because it underlies every sequential circuit. In a combinational circuit, signals flow strictly forward from inputs to outputs; there is no path by which an output can influence itself, so the moment the inputs change the outputs follow and nothing of the past survives. Introduce a wire that feeds an output back to an input and the situation changes qualitatively: the circuit now has a value that can sustain itself in a self-reinforcing loop. The two cross-coupled gates of an SR latch each hold the other in place — Q=1 keeps $\overline{Q}=0$Q​=0, and $\overline{Q}=0$Q​=0 keeps Q=1 — so the pair sits stably in either of two configurations until an input deliberately tips it into the other. Those two self-consistent configurations are the bistable states, the physical embodiment of the bit.

This is why memory is the dividing line between combinational and sequential logic, and why feedback is the mechanism. Every storage element in a computer — the one-bit latch, the byte-wide register, the megabit SRAM array — is at bottom a collection of these feedback loops, each holding one bit until told to change. The flip-flop "types" in this lesson are just different control wrappers around the same bistable core: the SR exposes raw set/reset, the D forces the inputs complementary for safe storage, the JK repurposes the spare input as a toggle. Recognising the shared bistable heart makes the family far less to memorise than it first appears.

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Clock Signals and Edge Triggering

The basic SR latch is asynchronous — it reacts the instant its inputs change. Real systems need state changes to happen at controlled, synchronised moments, so flip-flops are clocked: a periodic square-wave clock signal gates when they may respond.

Term	Meaning
Clock signal	A regular square wave that synchronises every flip-flop in a system
Level-triggered (latch)	Responds throughout the time the clock is HIGH (or LOW)
Edge-triggered (flip-flop)	Responds only at the instant the clock transitions
Rising (positive) edge	The clock's $0 \to 1$0→1 transition
Falling (negative) edge	The clock's $1 \to 0$1→0 transition

Edge-triggered flip-flops are strongly preferred over level-triggered latches because they sample their inputs at a single, well-defined instant. This makes timing predictable: every flip-flop captures its input at the same edge, the combinational logic between flip-flops has the whole clock period to settle (recall propagation delay from the logic-circuits lesson), and transient glitches that occur between edges are simply ignored. The clock period is chosen to exceed the worst-case combinational delay, guaranteeing inputs are stable when sampled.

Setup time, hold time and the synchronous discipline

For an edge-triggered flip-flop to capture its input reliably, the data must be stable for a short window around the clock edge: the setup time is the interval before the edge during which D must already be steady, and the hold time is the interval after the edge during which it must remain steady. A whole synchronous system is engineered so that the combinational logic feeding each flip-flop finishes changing — and settles — comfortably before the next edge, leaving the setup window clear. This is the deeper reason the clock period must exceed the worst-case combinational propagation delay: the period has to accommodate the slowest logic path plus the setup time of the receiving flip-flop. Shorten the logic (by the minimisation of earlier lessons) and you can shorten the period — i.e. raise the clock frequency — which is the concrete link between Boolean simplification and processor speed.

If the data does change inside the setup/hold window — as can happen when an asynchronous external signal (a button press, a signal from another clock domain) arrives at an arbitrary moment — the flip-flop can enter a metastable state: its output hovers at an undefined level between 0 and 1 for an unpredictable time before eventually settling randomly to one or the other. Metastability is the practical hazard that the synchronous, edge-triggered discipline exists to avoid, and it is why external inputs are passed through synchroniser flip-flops before the rest of the system trusts them. You will not be asked to calculate setup times, but understanding that flip-flops need their inputs stable around the edge — and that violating this causes unpredictable behaviour — is exactly the kind of applied reasoning that distinguishes a strong answer on clocking.

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The D-Type Flip-Flop

The D-type (data) flip-flop is the workhorse of digital systems. It has one data input D and a clock input CLK.

Behaviour: on the active clock edge, Q takes the value of D; at every other time Q holds its previous value.

D	CLK	Q (next state)
0	↑ rising edge	0
1	↑ rising edge	1
X	no edge	Q (unchanged)

(Here X means "don't care": with no clock edge, D is ignored entirely.)

The D-type's great virtue is that it eliminates the forbidden state: with only one data input, the $S=R=1$S=R=1 situation can never arise. It is built from an SR (or gated SR) flip-flop by driving $S=D$S=D and $R=\overline{D}$R=D through a single inverter, so S and R are always complementary and the illegal combination is structurally impossible:

flowchart LR
    D((D)) --> S["S = D"]
    D --> NOT{{"NOT"}}
    NOT --> R["R = D̄"]
    S --> SR[["Clocked SR flip-flop"]]
    R --> SR
    CLK((CLK)) --> SR
    SR --> Q["Q"]

Because one D-type cleanly stores one bit on each clock edge, it is the standard register cell and memory cell, and the building block of the shift registers below.

Worked trace: a D-type capturing changing data

The "samples only at the edge" behaviour is best seen by letting D wobble between edges and watching Q change only at the rising edges. Suppose the data and clock evolve as follows (Q starts at 0):

Time	D	Clock event	Q after
t1	1	rising edge ↑	1 (captures D=1)
t2	0	clock high, no edge	1 (ignores D)
t3	0	rising edge ↑	0 (captures D=0)
t4	1	clock low, no edge	0 (ignores D)
t5	1	rising edge ↑	1 (captures D=1)
t6	0	clock low, no edge	1 (ignores D)

At t2 and t4 the data input changes, but Q does not budge — it only updates at the rising edges (t1, t3, t5), each time taking whatever value D held at that instant. This is the essence of synchronous storage: the register's contents are a snapshot of the data taken once per clock period, immune to whatever the data does in between. Contrast a transparent (level-triggered) latch, which would have let Q follow D throughout the clock-high phase — exactly the unpredictability edge triggering removes.

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