Flip-Flops

Flip-flops are sequential logic circuits — unlike combinational circuits (gates), their output depends not only on the current inputs but also on the previous state. Flip-flops are the fundamental building blocks of memory, registers, and counters in digital systems.

---

Combinational vs Sequential Logic

Type	Output depends on	Memory?	Examples
Combinational	Current inputs only	No	AND, OR, NOT gates, adders
Sequential	Current inputs AND previous state	Yes	Flip-flops, registers, counters

Key Term: A flip-flop stores one bit of information. It has two stable states (0 and 1) and can be set to either state by applying appropriate inputs.

---

The SR Flip-Flop (Set-Reset)

The SR flip-flop has two inputs: S (Set) and R (Reset), and two outputs: Q and NOT Q (the complement of Q).

Behaviour:

S	R	Q (next state)	Description
0	0	Q (no change)	Outputs remain in their current state
0	1	0	Reset: Q becomes 0
1	0	1	Set: Q becomes 1
1	1	Invalid	Not allowed — both outputs would be forced to the same value

Construction from NOR gates: An SR flip-flop can be built from two cross-coupled NOR gates:

S ---+         +--- Q
     |--- NOR -|
     +----+    |
          |    +---+
     +----+        |
     |--- NOR -----+--- NOT Q
R ---+

Construction from NAND gates: An SR flip-flop can also be built from two cross-coupled NAND gates (with active-low inputs — S and R are inverted).

Exam Tip: The invalid state (S=1, R=1) is a key point in exam questions. You must explain why this state is problematic: it creates an ambiguous output where both Q and NOT Q would be the same value, violating the requirement that they are always complements.

---

Clock Signals and Edge Triggering

In practice, flip-flops are clocked — they only change state at specific moments determined by a clock signal.

Concept	Detail
Clock signal	A periodic square wave that synchronises all flip-flops in a circuit
Level-triggered	The flip-flop responds while the clock is HIGH (or LOW)
Edge-triggered	The flip-flop responds only at the moment of transition (rising edge or falling edge)
Rising edge	The transition from 0 to 1
Falling edge	The transition from 1 to 0

Edge-triggered flip-flops are preferred because they change state at a precise instant, making the circuit more predictable and reliable.

---

The D-Type Flip-Flop (Data Flip-Flop)

The D-type flip-flop is the most widely used flip-flop. It has a single data input D and a clock input CLK.

Behaviour: On the active clock edge, the output Q takes the value of D. At all other times, Q holds its previous value.

D	CLK (edge)	Q (next state)
0	Rising edge	0
1	Rising edge	1
X	No edge	Q (no change)

Where X means "don't care" — when there is no clock edge, the input D is ignored.

Key Properties:

• Stores one bit — whatever was on D at the clock edge is remembered
• Eliminates the invalid state — there is only one data input, so S=R=1 cannot occur
• Used in registers — a group of D-type flip-flops stores a multi-bit value

Circuit construction: A D-type flip-flop can be made from an SR flip-flop by connecting D to S and NOT D to R.

---

The JK Flip-Flop

The JK flip-flop solves the invalid state problem of the SR flip-flop differently. It has inputs J and K (analogous to S and R) and a clock.