The Fetch-Decode-Execute Cycle

The Fetch-Decode-Execute (FDE) cycle is the fundamental operating process of a processor. Every instruction a CPU runs goes through these three stages. For the OCR H446 exam you must be able to describe each stage in detail, explain the role of each register at every step, and discuss the effect of the clock speed on performance.

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Overview of the FDE Cycle

The FDE cycle is a continuous loop that the processor repeats for every instruction:

  +-------+      +--------+      +---------+
  | FETCH | ---> | DECODE | ---> | EXECUTE |
  +-------+      +--------+      +---------+
       ^                              |
       +------------------------------+

1. Fetch — the next instruction is retrieved from main memory.
2. Decode — the Control Unit interprets the instruction.
3. Execute — the instruction is carried out.

The cycle then repeats with the next instruction.

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The Fetch Stage

During the Fetch stage the processor retrieves the next instruction from memory. Here is what happens step by step:

Step	Action	Registers Involved
1	The contents of the PC are copied to the MAR	PC -> MAR
2	The address in the MAR is placed on the address bus	MAR -> Address Bus
3	The Control Unit sends a memory read signal along the control bus	CU -> Control Bus
4	The data at that memory address is transferred via the data bus to the MDR	Memory -> Data Bus -> MDR
5	The contents of the MDR are copied to the CIR	MDR -> CIR
6	The PC is incremented by 1 (to point to the next instruction)	PC = PC + 1

Exam Tip: Step 6 (incrementing the PC) typically happens at the same time as the memory read in step 4, because the PC and the memory system are separate hardware. State this if asked about timing. Note: the PC may be changed again during the Execute stage if the instruction is a branch.

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The Decode Stage

During the Decode stage the Control Unit (CU) examines the instruction held in the CIR and determines what operation needs to be performed.

Step	Action
1	The CU splits the instruction into the opcode (operation code) and the operand (data or address)
2	The CU interprets the opcode to determine the type of operation (e.g. load, add, store, branch)
3	The CU identifies which components are needed (ALU, memory, I/O) and generates the appropriate control signals
4	If the operand refers to a memory address, the address may be placed in the MAR ready for the Execute stage

Instruction Format

An instruction typically consists of two parts:

+----------+----------+
|  Opcode  | Operand  |
+----------+----------+

• Opcode — specifies the operation to perform (e.g. ADD, LOAD, STORE, BRANCH).
• Operand — provides the data or address needed by the instruction. This could be an actual value (immediate addressing) or a memory address (direct addressing).

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The Execute Stage

During the Execute stage the instruction is carried out. The exact actions depend on the type of instruction:

Arithmetic / Logic Operations

Step	Action
1	The operand value (or the value fetched from the address specified by the operand) is sent to the ALU
2	The ALU performs the operation (e.g. ADD, SUB, AND, OR, NOT)
3	The result is stored in the Accumulator (ACC)
4	Status flags may be updated (e.g. zero flag, carry flag, overflow flag)

Data Transfer Operations (LOAD / STORE)

LOAD:

1. The operand (memory address) is copied to the MAR.
2. A memory read signal is sent.
3. The data is transferred from memory via the data bus to the MDR.
4. The MDR value is copied to the ACC.

STORE:

1. The operand (memory address) is copied to the MAR.
2. The value in the ACC is copied to the MDR.
3. A memory write signal is sent.
4. The data in the MDR is written to the memory location specified by the MAR.

Branch Operations

Type	Action
Unconditional branch	The operand (target address) is copied directly into the PC, so the next Fetch will retrieve the instruction at that address
Conditional branch	The CU checks the relevant status flag (e.g. zero flag). If the condition is met, the operand is loaded into the PC. If not, the PC is left unchanged and execution continues sequentially

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Detailed Walkthrough — Example

Consider the instruction ADD 50 (add the value at memory address 50 to the accumulator).