Pipelining

Pipelining is a technique used in processor design to increase instruction throughput by overlapping the execution stages of multiple instructions. For the OCR H446 exam, you must understand how pipelining works, its advantages, the types of hazards that can occur, and how branch prediction addresses control hazards.

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How Pipelining Works

In a non-pipelined processor, each instruction must complete all stages (Fetch, Decode, Execute) before the next instruction begins. This leaves parts of the CPU idle during each stage.

Without pipelining (sequential execution):

Time:       1   2   3   4   5   6   7   8   9
Instr 1:    F   D   E
Instr 2:                F   D   E
Instr 3:                            F   D   E

Three instructions take 9 clock cycles.

With pipelining:

Time:       1   2   3   4   5
Instr 1:    F   D   E
Instr 2:        F   D   E
Instr 3:            F   D   E

Three instructions take only 5 clock cycles. After the pipeline is full, one instruction completes every clock cycle.

The Principle

Pipelining divides the processor into separate stages, each handled by dedicated hardware. While one instruction is being executed, the next is being decoded, and a third is being fetched — all at the same time.