Processor Types

This lesson covers the different types of processors you need to know for OCR H446: CISC vs RISC, multi-core processors, parallel processing, co-processors and GPUs. You must be able to compare these types and explain when each is suitable.

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CISC — Complex Instruction Set Computer

A CISC processor has a large, varied instruction set where individual instructions can perform complex multi-step operations.

Characteristics of CISC

Feature	Detail
Instruction set	Large — hundreds of different instructions
Instruction length	Variable — instructions can be different numbers of bytes
Instruction complexity	Single instructions can perform complex tasks (e.g. multiply and store in one instruction)
Clock cycles per instruction	Variable — complex instructions may take many clock cycles
Addressing modes	Many different addressing modes available
Registers	Fewer general-purpose registers
Hardware	Complex — uses microcode (micro-programs) to implement complex instructions
Compiler complexity	Simpler — the compiler has many powerful instructions to choose from

Examples

• Intel x86 / x86-64 processors used in most desktop PCs and laptops.
• AMD processors based on the x86-64 architecture.

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RISC — Reduced Instruction Set Computer

A RISC processor has a small, highly optimised instruction set where each instruction performs a simple operation and (ideally) executes in a single clock cycle.

Characteristics of RISC

Feature	Detail
Instruction set	Small — typically fewer than 100 instructions
Instruction length	Fixed — all instructions are the same number of bytes
Instruction complexity	Each instruction performs a single, simple operation
Clock cycles per instruction	Ideally one clock cycle per instruction
Addressing modes	Fewer addressing modes
Registers	Many general-purpose registers (often 32 or more)
Hardware	Simpler — instructions are hardwired, no microcode needed
Compiler complexity	More complex — the compiler must break down complex operations into sequences of simple instructions

Examples

• ARM processors used in smartphones, tablets and the Raspberry Pi.
• Apple M-series chips (ARM-based RISC).
• MIPS processors used in some embedded systems.

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CISC vs RISC Comparison

Feature	CISC	RISC
Number of instructions	Many (hundreds)	Few (under 100)
Instruction length	Variable	Fixed
Cycles per instruction	Multiple	Ideally one
Registers	Fewer	Many (32+)
Pipelining efficiency	Harder (variable-length instructions)	Easier (fixed-length, predictable)
Power consumption	Higher	Lower
Code density	Higher (fewer instructions needed)	Lower (more instructions for same task)
Compiler complexity	Simpler	More complex
Microcode	Yes	No (hardwired)
Typical use	Desktop PCs, servers	Mobile devices, embedded systems

Modern Convergence

Modern x86 (CISC) processors internally translate complex instructions into micro-operations (micro-ops) that are executed by a RISC-like core. This means the distinction between CISC and RISC has blurred — the external interface is CISC, but the internal execution engine is essentially RISC.

Exam Tip: If asked to compare CISC and RISC, provide at least four clear differences in a table and then mention the modern convergence. State that RISC is better suited to pipelining because of its fixed-length instructions.

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Multi-Core Processors

A multi-core processor contains two or more independent processing units (cores) on a single chip. Each core can fetch, decode and execute its own stream of instructions independently.

How Multi-Core Improves Performance

Aspect	Explanation
True parallelism	Each core executes a separate thread simultaneously
Shared cache	Cores often share L2 or L3 cache, enabling fast data sharing
Multi-tasking	The OS can assign different processes or threads to different cores

Limitations of Multi-Core

Limitation	Explanation
Software must be multi-threaded	If a program is single-threaded, it can only use one core — the extra cores are idle
Amdahl's Law	The maximum speedup is limited by the fraction of the program that must run sequentially. If 10% of a program is sequential, the maximum speedup with infinite cores is only 10x
Overhead	Managing threads, synchronisation and communication between cores adds overhead
Diminishing returns	Doubling the number of cores does not double performance

Common Multi-Core Configurations