AQA A-Level Computer Science: Computer Architecture

A processor executes machine-code instructions using the Fetch-Decode-Execute (FDE) cycle. It contains several special-purpose registers, including the Program Counter (PC), the Memory Address Register (MAR), the Memory Data Register (MDR), the Current Instruction Register (CIR) and the Accumulator (ACC).

(a) State the role of each of the following registers: PC, MAR, MDR, CIR and ACC. [5 marks]

(b) Using register transfer notation, describe, step by step, the transfers that take place during one complete FETCH phase of the FDE cycle. For each step, name the bus involved where appropriate. [5 marks]

(c) The processor currently has a 16-bit address bus. Explain the effect on the amount of directly addressable memory of widening the address bus to 18 bits. [2 marks]

The following scenario was written for this exercise.

A company is designing the processor for a pair of battery-powered wireless earbuds. The earbuds run a single fixed program that continuously decodes an audio stream and cancels background noise in real time. The design team must choose between a RISC processor and a CISC processor. One engineer argues that "CISC instructions are more powerful, so a CISC chip will always be the better choice".

Discuss the relative merits of a RISC and a CISC processor for these earbuds, and conclude with a justified recommendation. [9 marks]

The following memory contents and instructions were written for this exercise.

A processor supports four addressing modes. In the assembly notation used here, # marks an immediate value, a plain number is a direct address, parentheses mark indirect addressing, and ,X marks indexed addressing (the contents of the index register IX are added to the operand). The relevant memory contents and the index register are:

Address	Contents
40	90
41	44
42	40
90	17

IX = 2, and the accumulator ACC starts at 0.

For each of the four instructions below, determine the effective address (where one applies) and the value loaded into ACC. Show your working.

LDA #42        # immediate
LDA 42         # direct
LDA (42)       # indirect
LDA 40,X       # indexed

[6 marks]

A processor is connected to main memory by a system bus made up of three separate buses: the address bus, the data bus and the control bus.

(a) State what is carried by each of the three buses. [3 marks]

(b) Explain how the width of the address bus and the width of the data bus each affect what the computer can do. [2 marks]

A processor uses pipelining to improve its performance.

Explain what is meant by pipelining and how it increases the rate at which instructions are completed. You may refer to the fetch, decode and execute stages in your answer. [4 marks]

A Graphics Processing Unit (GPU) contains a very large number of relatively simple cores, whereas a typical CPU has a small number of powerful cores.

(a) Explain why a GPU is well suited to tasks that apply the same operation to large amounts of data. [2 marks]

(b) State one example of a task, other than rendering graphics, for which a GPU is well suited. [1 mark]