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OCR A-Level Computer Science: Boolean Algebra & Logic

6 exam-style questions with full mark schemes and model answers. Write your own answer and the AI examiner marks it against the mark scheme.

Question 112 marksConstruct

A logic designer is working with three Boolean inputs AAA, BBB and CCC. Answer each part, showing your working.

(a) Construct the complete truth table for the expression

Q=AB+ACQ = \overline{A} \cdot B + A \cdot \overline{C}Q=AB+AC

Your table must have one row for each of the eight input combinations of AAA, BBB and CCC. [4]

(b) A different circuit implements the expression

P=AB+ABCP = A \cdot B + A \cdot \overline{B} \cdot CP=AB+ABC

Simplify PPP to its minimal form using the laws of Boolean algebra. You must name the law applied at each step. [5]

(c) Assuming only 2-input gates (plus inverters) are available, state how many gates the original expression PPP in part (b) requires, how many your simplified form requires, and hence how many gates are saved. [3]

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Question 29 marksDerive

The following function was written for this exercise.

A Boolean function of four variables AAA, BBB, CCC, DDD is true (1) for exactly the following minterms and false (0) for all others:

F=m(0, 2, 8, 10, 11, 14, 15)F = \sum m(0,\ 2,\ 8,\ 10,\ 11,\ 14,\ 15)F=m(0, 2, 8, 10, 11, 14, 15)

(Here each minterm number is the denary value of the 4-bit pattern ABCDABCDABCD; for example minterm 10=101010 = 101010=1010 means A=1,B=0,C=1,D=0A{=}1, B{=}0, C{=}1, D{=}0A=1,B=0,C=1,D=0.)

(a) Plot FFF on a Karnaugh map. Draw the map as a 4x4 grid with the rows labelled by ABABAB and the columns labelled by CDCDCD, both in Gray-code order (00,01,11,1000, 01, 11, 1000,01,11,10). [3]

(b) Use the K-map to derive the minimal sum-of-products (SOP) expression for FFF. For each group you form, state its size (1, 2, 4 or 8) and which variable(s) it eliminates. [4]

(c) The canonical SOP for FFF (one product term per minterm) would use seven 4-input AND terms feeding a 7-input OR. Estimate roughly how many gate-inputs your minimal SOP saves compared with this canonical form. [2]

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Question 36 marksApply

A NOR-style sub-circuit computes the negated expression

Q=A+BCQ = \overline{A + B \cdot C}Q=A+BC

Apply De Morgan's laws to transform QQQ into an equivalent expression in which the only negations are over single variables (i.e. push the overbar inwards until no overbar spans more than one variable). Then verify the equivalence of your result with the original by constructing a truth table for all eight combinations of AAA, BBB and CCC. [6]

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Question 45 marksExplain

A full adder adds three single-bit inputs: two operand bits AAA and BBB together with a carry-in CinC_{in}Cin. It produces a sum output SSS and a carry-out output CoutC_{out}Cout.

(a) Give the Boolean expressions for the sum SSS and the carry-out CoutC_{out}Cout of a full adder in terms of AAA, BBB and CinC_{in}Cin. [2]

(b) A circuit must add two 8-bit binary numbers. Explain why full adders (rather than half adders) are required for this, referring to carry propagation between bit positions. [3]

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Question 54 marksExplain

A D-type flip-flop is an edge-triggered sequential logic component with a data input DDD, a clock input, and an output QQQ.

Explain how a D-type flip-flop stores one bit of data, making clear the role of the clock (edge-triggering), and state why D-type flip-flops are the building block of registers. [4]

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Question 63 marksIdentify

The following truth table was written for this exercise.

A single 2-input logic gate has the truth table below.

AAABBBQQQ
001
011
101
110

(a) Identify the single standard gate that this truth table represents, and give its Boolean expression. [1]

(b) This gate is described as a universal gate. State what "universal" means in this context and why it is a useful property. [2]

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