AQA A-Level Computer Science: Computer Architecture — Complete Revision Guide (7517)

Computer architecture is where the abstract world of programs meets the physical reality of silicon, and it is one of the highest-yield topics in the AQA A-Level Computer Science (7517) specification because so much of it can be revised to a point of near-certainty. The hardware and processor content sits in spec area 4.7 (the structure and role of the processor and its components), while the Boolean algebra and logic-circuit material is drawn from areas 4.6.4 and 4.6.5 (Boolean algebra and logic gate circuits). Together they explain how a processor fetches and executes instructions, how those instructions are encoded and addressed, why different processor designs make different trade-offs, and how the logic gates beneath everything are described and combined into useful circuits such as adders and flip-flops.

This material is examined across both written papers. Paper 1 (on-screen, 40% of the A-Level) tends to test the applied edges — interpreting machine-code instructions and addressing modes, or reasoning about how a particular instruction moves through the fetch-decode-execute cycle in the context of code you are working with. Paper 2 (written, also 40%) is where the bulk of this topic lives: describing the cycle stage by stage, comparing CISC and RISC, explaining pipelining and its hazards, simplifying Boolean expressions, and constructing or tracing logic circuits. The final 20% is the Non-Exam Assessment (NEA) programming project; architecture is not assessed there directly, but understanding how a processor executes code informs sensible design and efficiency decisions in your solution.

This guide works through every lesson in the LearningBro Computer Architecture course in a deliberate order: starting from the two great architectural blueprints, descending into the processor's internal components and its operating cycle, then widening out to instruction sets, performance techniques, and the physical periphery, before finishing with the Boolean logic and digital circuits that sit underneath it all. Use it to give your revision a clear narrative spine and to pinpoint the precise places where examiners expect exact terminology.

Guide Overview

• Von Neumann and Harvard architecture
• The processor: registers, buses and the FDE cycle
• Instruction sets and addressing modes
• CISC vs RISC architectures
• Pipelining
• Parallel processing and multi-core systems
• Input/output devices and interfaces
• Secondary storage technologies
• Boolean algebra and logic gate circuits
• Adder circuits and flip-flops

Von Neumann and Harvard Architecture

Every processor question rests on understanding the two foundational designs, set out in the Von Neumann and Harvard architecture lesson. The Von Neumann architecture stores both program instructions and data in the same memory, accessed over a shared bus. Its defining feature — the stored-program concept — is that instructions are themselves just data held in memory, which is what makes general-purpose, reprogrammable computers possible. Its defining weakness is the Von Neumann bottleneck: because instructions and data travel along the same bus, the processor cannot fetch an instruction and transfer data in the same instant, capping throughput.

The Harvard architecture uses physically separate memories and separate buses for instructions and data, so an instruction fetch and a data access can happen simultaneously. This raises throughput and gives more predictable timing, which is why Harvard designs are favoured in embedded systems and digital signal processors. The exam-relevant nuance is that most modern general-purpose processors are best described as a modified Harvard architecture: they keep separate Level 1 caches for instructions and data (the Harvard idea) on top of a single unified main memory (the Von Neumann idea), capturing the speed of one and the flexibility of the other.

A reliable pitfall is to state only that the two differ in "having separate memory" without naming the consequence — the parallel fetch capability and the avoidance of the bottleneck. Tie the structural difference to its performance effect and the comparison marks follow.

The Processor: Registers, Buses and the Fetch-Decode-Execute Cycle

The processor lesson is the single most examined piece of the whole topic, and it must be learned to the level where you can recite it precisely. The processor's main components are the Arithmetic Logic Unit (ALU), which performs arithmetic and logical operations; the Control Unit (CU), which decodes instructions and coordinates the other components using control signals; the clock, which synchronises operations; and a set of registers — small, extremely fast storage locations inside the processor.

Register	Full name	Role
PC	Program Counter	Holds the address of the next instruction to fetch
MAR	Memory Address Register	Holds the address being read from or written to
MDR	Memory Data Register	Holds data/instruction just read from, or about to be written to, memory
CIR	Current Instruction Register	Holds the instruction currently being decoded and executed
ACC	Accumulator	Holds intermediate results of ALU operations

The components communicate over three buses. The address bus carries the target memory address and is unidirectional from the processor; its width sets the maximum addressable memory (an n-bit address bus can address 2ⁿ locations). The data bus carries the actual data and is bidirectional; its width sets how much data moves per transfer. The control bus carries control and timing signals such as read/write and clock signals, and is effectively bidirectional across its individual lines.

The fetch-decode-execute cycle is the heart of it, and AQA expects a register-level description:

1. Fetch — the address in the PC is copied to the MAR; a read signal is sent on the control bus; the instruction at that address is placed on the data bus and loaded into the MDR; it is then copied to the CIR; and the PC is incremented to point to the next instruction.
2. Decode — the Control Unit decodes the instruction in the CIR, separating the opcode (which operation) from the operand (the data or address).
3. Execute — the processor carries out the instruction, which may mean an ALU operation with the result stored in the accumulator, a data transfer, or updating the PC for a branch.

Three factors affecting processor performance recur in the exam: clock speed (more cycles per second, but with practical heat limits), the number of cores (more cores can execute more instruction streams concurrently), and cache size and levels (larger, faster caches reduce slow trips to main memory). The standard pitfall is describing the fetch stage without the register transfers — examiners want PC → MAR, read, MDR → CIR, increment PC, in that order. Another is forgetting that the PC is incremented during fetch, not at the end of execute.

Instruction Sets and Addressing Modes

The instruction sets and addressing modes lesson explains how instructions are encoded and how their operands locate data. A machine-code instruction divides into an opcode (specifying the operation and the addressing mode) and one or more operands. The specification requires you to understand two addressing modes in particular: immediate addressing, where the operand is the value to be used directly, and direct addressing, where the operand is the address of the value in memory. You should be able to work through how each mode changes what the processor does during the execute phase — immediate uses the operand as-is, while direct triggers a further memory access to retrieve the value at that address.

The exam-relevant point is the trade-off: immediate addressing is fast (no extra memory access) but the value is fixed at the point the instruction is written; direct addressing adds a memory access but lets the same instruction operate on whatever value currently sits at that address. A common pitfall is mixing up the two — students sometimes describe direct addressing as "the operand is the data", which is actually immediate addressing. Anchor it firmly: in direct addressing the operand is a pointer to the data; in immediate addressing the operand is the data.

CISC vs RISC Architectures

The CISC vs RISC lesson compares two design philosophies for instruction sets. CISC (Complex Instruction Set Computer) processors offer a large, rich instruction set in which a single instruction can perform several low-level operations — load, compute, store — in one instruction. This keeps programs shorter in terms of instruction count and historically eased assembly programming, but instructions vary in length and take varying numbers of clock cycles, complicating the hardware. The x86 family used in most desktops and laptops is CISC-based.

RISC (Reduced Instruction Set Computer) processors use a small set of simple, fixed-length instructions, each typically executing in a single clock cycle. Complexity moves into the compiler, which breaks tasks into many simple instructions. The payoffs are simpler control hardware, lower power consumption, and instructions that pipeline cleanly. ARM processors, used in most smartphones and tablets, are RISC-based.

Feature	CISC	RISC
Instruction set	Large, complex, varied length	Small, simple, fixed length
Cycles per instruction	Variable, often many	Usually one
Work per instruction	More (multi-step)	Less (single-step)
Pipelining	Harder (variable lengths)	Easier (uniform instructions)
Power efficiency	Lower	Higher
Typical use	Desktops/laptops (x86)	Mobile/embedded (ARM)

The pitfall to avoid is a one-sided answer. A top-band response gives matched points for both sides and ideally notes the modern reality that many CISC processors internally translate complex instructions into RISC-like micro-operations, blurring the historical distinction. Linking RISC's uniform instructions to why it pipelines more easily sets up the next lesson directly.

Pipelining

The pipelining lesson explains a key performance technique: overlapping the stages of the fetch-decode-execute cycle so that, while one instruction is executing, the next is being decoded and the one after that is being fetched. Pipelining increases instruction throughput without raising the clock speed, because the processor is no longer idle in stages it is not currently using. The classic analogy is a production line where each station works on a different unit simultaneously.

The exam expects you to know the pipeline hazards that reduce the ideal speed-up. Data hazards occur when an instruction needs the result of an earlier instruction that has not yet completed its journey through the pipeline. Control hazards (branch hazards) arise from branch instructions, because the processor may have already fetched instructions that should not now be executed if the branch is taken. Structural hazards occur when two instructions need the same hardware resource at the same time. You should be able to explain that branches in particular force the pipeline to be flushed and refilled, wasting cycles. A common pitfall is claiming pipelining "makes each instruction faster" — it does not; each individual instruction takes the same time, but more instructions complete per unit time. Throughput, not per-instruction latency, is the correct framing.

Parallel Processing and Multi-Core Systems

The parallel processing and multi-core systems lesson covers how performance is scaled by doing more than one thing at once. A multi-core processor contains several independent processing units (cores) on one chip, each capable of executing its own instruction stream, so genuinely concurrent execution is possible. The specification expects you to understand that the speed-up from adding cores is not linear: not all tasks divide neatly into independent parallel parts, and there are overheads in splitting work, coordinating cores, and recombining results. Tasks that are inherently sequential — where each step depends on the previous one — gain little from extra cores.

You should be able to discuss the classification of parallel approaches, including SIMD (Single Instruction, Multiple Data), where one instruction operates on many data items at once (as in a GPU performing the same operation across many pixels), and MIMD (Multiple Instruction, Multiple Data), where multiple cores execute different instructions on different data (as in a typical multi-core CPU running separate threads). The standard pitfall is to assert that doubling the cores doubles the speed; always qualify with the dependence on how parallelisable the workload is and the coordination overhead involved.

Input/Output Devices and Interfaces

The input/output devices and interfaces lesson widens the view to how the processor communicates with the outside world. Input devices convert real-world data into a form the computer can process — keyboards, mice, microphones, scanners and sensors — while output devices convert processed data into a usable form, such as monitors, printers, speakers and actuators. The specification expects you to be able to describe the principles of operation of a small number of named devices and to reason about which device suits a given application and why.

The interface concepts that matter are how peripherals connect and communicate with the processor, including the role of device controllers and the standard buses and ports that handle data transfer. A useful exam habit is to relate the device choice to its data characteristics — for example, why a particular sensor produces analogue data that must be converted to digital before processing. The pitfall here is vague, list-style answers; questions reward an explanation of how a device works or why it is appropriate, not merely naming it.

Secondary Storage Technologies

The secondary storage technologies lesson covers non-volatile, long-term storage and the three technologies you must compare. Magnetic storage, such as the hard disk drive, records data as magnetised regions on spinning platters read by a moving head; it offers high capacity at low cost per gigabyte but is comparatively slow and mechanically fragile. Optical storage — CDs, DVDs and Blu-ray — uses a laser to read pits and lands on a disc surface; it is cheap and portable but limited in capacity and slow to write. Solid-state storage, such as SSDs and flash drives, uses NAND flash memory with no moving parts, giving very fast access, durability and low power draw, at a higher cost per gigabyte and with a finite number of write cycles.

Technology	Mechanism	Strengths	Weaknesses
Magnetic (HDD)	Magnetised regions on spinning platters	High capacity, low cost/GB	Slow, mechanically fragile
Optical (CD/DVD/Blu-ray)	Laser reads pits and lands	Cheap, portable	Low capacity, slow writes
Solid-state (SSD/flash)	NAND flash, no moving parts	Very fast, durable, low power	Higher cost/GB, finite write cycles

A frequent pitfall is conflating secondary storage with main memory (RAM). Secondary storage is non-volatile and retains data without power; RAM is volatile working memory. Make the volatility distinction explicit, and remember the headline trade-off triangle of capacity, speed and cost that distinguishes the three technologies.

Boolean Algebra and Logic Gate Circuits

The Boolean algebra and logic gate circuits lesson descends to the logic beneath the hardware, drawing on spec areas 4.6.4 and 4.6.5. You must know the standard gates and their behaviour: AND (output 1 only when all inputs are 1), OR (output 1 when at least one input is 1), NOT (inverts the input), NAND (the inverse of AND), NOR (the inverse of OR), and XOR (output 1 when the inputs differ). You should be able to construct truth tables for combinations of gates and to translate freely between a logic circuit, its Boolean expression, and its truth table.

Boolean algebra lets you simplify expressions, and the specification expects fluency with the standard laws. De Morgan's laws are the most heavily tested: NOT(A AND B) = (NOT A) OR (NOT B), and NOT(A OR B) = (NOT A) AND (NOT B). Alongside these you should apply the commutative, associative and distributive laws, the identity and complement laws, and the absorption laws to reduce an expression to its simplest form.

Law	Form
Commutative	A + B = B + A; A · B = B · A
Associative	(A + B) + C = A + (B + C)
Distributive	A · (B + C) = A · B + A · C
Identity	A + 0 = A; A · 1 = A
Complement	A + Ā = 1; A · Ā = 0
Absorption	A + A · B = A
De Morgan's	(A · B)′ = A′ + B′; (A + B)′ = A′ · B′

The defining pitfall is misapplying De Morgan's law by negating the terms but forgetting to swap the operator (AND becomes OR and vice versa) — both changes must happen together. When simplifying, show each law you apply step by step; examiners award method marks for a correct sequence even if the final form is not fully reduced.

Adder Circuits and Flip-Flops

The adder circuits and flip-flops lesson shows how gates are combined into the building blocks of arithmetic and memory. A half adder adds two single-bit inputs and produces a sum (the XOR of the inputs) and a carry (the AND of the inputs), but it has no way to accept a carry coming in from a previous column. A full adder fixes this by accepting a third input — the carry-in — and can be built from two half adders plus an OR gate; chaining full adders together produces a circuit that adds multi-bit binary numbers, which is exactly how a processor performs addition.

A flip-flop stores a single bit. The specification focuses on the D-type flip-flop, which captures the value on its data input and holds it, changing state only on the active edge of a clock signal. Because each flip-flop holds one bit and synchronises to the clock, flip-flops are the basis of registers and other fast on-chip storage. The exam-relevant link is that this closes the loop back to the start of the topic: the registers in the fetch-decode-execute cycle are built from flip-flops, and the ALU's arithmetic is built from adder circuits. A common pitfall is to describe a flip-flop's output as changing continuously with its input; emphasise that the D-type changes only on the clock edge, which is precisely what makes synchronous, predictable storage possible.

This material threads through the whole qualification. The binary arithmetic that adder circuits perform connects directly to the data representation course, and the abstraction principles that let us reason about a processor without tracking every transistor recur throughout the theory of computation course. For the complete topic with worked examples, circuit traces and exam-style questions, study the AQA A-Level Computer Science: Computer Architecture course, and position it within your wider revision using the A-Level Computer Science (AQA) learning path.

Next Steps

Lock down the fetch-decode-execute cycle first, to the point where you can write out the register transfers from memory — it is the most frequently examined piece and underpins instruction sets, addressing modes and pipelining. Then secure the comparison topics (Von Neumann vs Harvard, CISC vs RISC, the storage technologies) by always pairing a structural difference with its consequence, and drill Boolean simplification with the laws shown step by step, taking special care with De Morgan's. Finish by working through logic-circuit and adder questions until tracing a circuit feels routine, then move on to the next topic in the A-Level Computer Science (AQA) learning path.