Common CPU Components and Registers

This lesson provides a comprehensive overview of all the key CPU components and registers you need to know for OCR J277 Section 1.1.1. While earlier lessons introduced these individually, this lesson brings everything together and explores how the components interact.

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The Three Main CPU Components

1. The Arithmetic Logic Unit (ALU)

The ALU is the part of the CPU that performs all arithmetic and logical operations.

Arithmetic operations:

• Addition (+)
• Subtraction (-)
• Multiplication (*)
• Division (/)

Logical operations:

• Comparisons: equal to (==), not equal to (!=), greater than (>), less than (<)
• Boolean logic: AND, OR, NOT

Every calculation the computer performs — from adding numbers in a spreadsheet to determining whether a character in a game has collided with an obstacle — passes through the ALU.

The ALU receives data from registers (typically the accumulator) and sends results back to registers after processing.

2. The Control Unit (CU)

The Control Unit is the component that manages and coordinates all CPU activities. It does not process data itself — instead, it tells other components what to do and when.

The CU is responsible for:

Function	Description
Fetching	Sending signals to memory to retrieve the next instruction
Decoding	Interpreting the fetched instruction (splitting it into opcode and operand)
Coordinating	Sending control signals to the ALU, registers, memory, and I/O devices
Timing	Using the system clock to synchronise all operations

Think of the CU as a conductor in an orchestra — it does not play any instruments, but it ensures every musician (component) plays at the right time.

3. The Cache

Cache is a small, ultra-fast memory built into the CPU. It stores copies of the most frequently accessed data and instructions to reduce the time the CPU spends waiting for data from RAM.

Cache operates on the principle of locality of reference:

• Temporal locality: Data that has been accessed recently is likely to be accessed again soon.
• Spatial locality: Data stored near recently accessed data is likely to be needed next.

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Key Registers

Registers are tiny, extremely fast storage locations inside the CPU. They are the fastest type of memory in a computer because they are built directly into the CPU chip.

The Four Registers You Must Know

Register	Full Name	Width	Purpose
PC	Program Counter	Typically 32 or 64 bits	Holds the memory address of the next instruction to be fetched
MAR	Memory Address Register	Matches address bus width	Holds the address of the memory location to be read from or written to
MDR	Memory Data Register	Matches data bus width	Holds the data fetched from memory or data to be written to memory
ACC	Accumulator	Typically 32 or 64 bits	Stores the result of ALU calculations

How Registers Interact During the FDE Cycle

graph TD
  subgraph FETCH
    PC1["PC"] -->|copy address| MAR["MAR"]
    MAR -->|address bus| MEM["Memory"]
    MEM -->|data bus| MDR["MDR"]
    PC1 -->|increment| PCINC["PC + 1"]
  end
  subgraph DECODE
    MDR -->|instruction| CU["CU"]
    CU -->|splits into| OPS["opcode + operand"]
  end
  subgraph EXECUTE
    OPS --> EX{"Instruction type"}
    EX -->|arithmetic / logic| ALU["ALU result"] --> ACCo["ACC"]
    EX -->|store| ACCi["ACC"] --> MEMo["Memory (via MDR/MAR)"]
    EX -->|branch| ADDR["New address"] --> PCo["PC"]
  end

OCR Exam Tip: Be able to draw a labelled diagram showing the CPU components (ALU, CU, cache) and registers (PC, MAR, MDR, ACC) with arrows showing data flow. This is a common 4-6 mark question.

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Additional Registers (Extended Knowledge)

While OCR J277 focuses on the four registers above, you may encounter these in higher-mark questions:

Register	Purpose
CIR (Current Instruction Register)	Holds the instruction currently being decoded/executed
Status Register	Contains flags (e.g. overflow, zero, carry) set by the ALU after operations
Stack Pointer	Points to the top of the system stack in memory

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How It All Fits Together

Here is a summary of how all CPU components work together to execute a single instruction:

1. The CU reads the address from the PC and copies it to the MAR.
2. The CU sends a read signal along the control bus to main memory.
3. The instruction at the address is sent along the data bus to the MDR.
4. The CU decodes the instruction from the MDR.
5. If calculation is needed, the ALU performs it using data from the ACC or memory.
6. The result is stored in the ACC (or written to memory).
7. The PC is incremented to point to the next instruction.

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Summary

• The CPU contains three main components: ALU (calculations), CU (control and coordination), and cache (fast temporary storage).
• Four key registers: PC (next instruction address), MAR (memory address), MDR (memory data), ACC (calculation results).
• All components work together during the FDE cycle to process instructions.
• Understanding data flow between these components is essential for OCR J277 exam success.

OCR Exam Tip: Questions about CPU components often ask you to explain the purpose of a specific register or trace data flow through the CPU. Use register names precisely — marks are awarded for correct terminology.

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Worked Example: Executing an ADD Instruction Step by Step

The best way to lock in the roles of the ALU, CU, cache, PC, MAR, MDR and ACC is to walk every register through a single instruction. This worked example is the kind of trace OCR examiners reward heavily.

Scenario: The CPU is about to execute an ADD instruction whose opcode means "take the value at memory address 50 and add it to the accumulator". The instruction itself is stored at memory address 30. Before the cycle begins:

• PC = 30 (address of the ADD instruction)
• ACC = 7 (the current running total)
• The value at memory address 50 = 5

Step 1 — fetch starts. The Control Unit reads the PC, finds the value 30, and copies it into the MAR. A READ signal is asserted on the control bus. The MAR sends 30 across the address bus to memory.

Step 2 — the instruction arrives. Memory looks up the byte at address 30 (the ADD instruction) and places it on the data bus. The CPU latches it into the MDR. At the same time, the Control Unit increments the PC to 31 so it points to whatever instruction comes next.

Register	Value at end of Step 2
PC	31
MAR	30
MDR	ADD #50 (opcode + operand)
ACC	7

Step 3 — decode. The MDR contents are passed to the Control Unit, which splits the instruction into an opcode ("ADD from memory") and an operand (50). The CU determines that a memory fetch is needed to get the addend, then an ALU addition.

Step 4 — execute phase begins with a second memory read. The CU copies 50 into the MAR, asserts READ on the control bus, and the value 5 stored at address 50 travels back across the data bus into the MDR.

Register	Value at end of Step 4
PC	31
MAR	50
MDR	5
ACC	7