The Role of the Motherboard and Buses

This lesson covers the motherboard and the system bus (address bus, data bus, and control bus), as required by OCR J277 Section 1.1.1. Understanding how components communicate is essential for explaining how a computer system functions as a whole.

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The Motherboard

The motherboard is the main circuit board inside a computer. It is the physical foundation that connects all the components of a computer system together.

What Does the Motherboard Do?

Function	Description
Physical connections	Provides slots and sockets for the CPU, RAM, storage, and expansion cards
Communication pathways	Contains the buses (wires/traces) that allow components to send data to each other
Power distribution	Distributes electrical power from the power supply to all components
BIOS/UEFI chip	Contains the firmware needed to start the computer (boot process)

Key Connectors on a Motherboard

• CPU socket — where the processor is installed
• RAM slots (DIMM) — where memory modules are inserted
• PCIe slots — for expansion cards (graphics card, network card, sound card)
• SATA connectors — for connecting storage devices (HDDs, SSDs)
• USB headers — for connecting USB ports
• Power connectors — receive power from the PSU (power supply unit)

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The System Bus

The system bus is a collection of wires (also called traces on the motherboard) that carry signals between the CPU, memory, and other components. It consists of three separate buses:

1. The Address Bus

Property	Detail
Purpose	Carries the memory address that the CPU wants to access
Direction	Unidirectional — data flows only from the CPU to memory/devices
Width	Determines the maximum amount of memory the CPU can address

How address bus width affects memory:

The width of the address bus (measured in bits) determines how many unique memory addresses the CPU can access:

• A 16-bit address bus can address 2^16 = 65,536 memory locations (64 KB)
• A 32-bit address bus can address 2^32 = 4,294,967,296 memory locations (4 GB)
• A 64-bit address bus can address 2^64 memory locations (over 16 exabytes)

OCR Exam Tip: The formula for calculating addressable memory is: Number of addresses = 2^n, where n is the width of the address bus in bits.

2. The Data Bus

Property	Detail
Purpose	Carries data between the CPU, memory, and I/O devices
Direction	Bidirectional — data can flow in both directions
Width	Determines how much data can be transferred in one operation

How data bus width affects performance:

• A wider data bus means more data can be transferred per clock cycle.
• An 8-bit data bus can transfer 1 byte per cycle; a 64-bit data bus can transfer 8 bytes per cycle.
• A wider data bus generally improves system performance because less time is spent transferring data.

3. The Control Bus

Property	Detail
Purpose	Carries control signals that coordinate the activities of the computer
Direction	Bidirectional — signals flow both ways
Signals	Read, write, clock, interrupt, bus request, bus grant, reset

Key control signals:

Signal	Purpose
Read	Tells memory to send data to the CPU
Write	Tells memory to store data from the CPU
Clock	Synchronises all operations
Interrupt	A device signals that it needs attention
Bus request/grant	A device requests use of the bus
Reset	Restarts the system

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How the Three Buses Work Together

Here is what happens when the CPU wants to read data from memory:

1. The CPU places the memory address on the address bus.
2. The CPU sends a read signal on the control bus.
3. Memory receives the address and the read signal.
4. Memory places the requested data on the data bus.
5. The CPU reads the data from the data bus.

And when the CPU wants to write data to memory:

1. The CPU places the memory address on the address bus.
2. The CPU places the data to be written on the data bus.
3. The CPU sends a write signal on the control bus.
4. Memory receives the address, data, and write signal, and stores the data at the specified address.

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Bus Width and System Performance

Bus	Wider Width Means...
Address bus	More memory locations can be addressed
Data bus	More data transferred per cycle (faster throughput)
Control bus	More control signals can be sent (more complex operations)

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Summary

• The motherboard is the main circuit board connecting all components (OCR J277 1.1.1).
• The system bus consists of three buses: address, data, and control.
• Address bus: unidirectional, carries memory addresses; width determines max addressable memory (2^n).
• Data bus: bidirectional, carries data; width determines how much data can be transferred per cycle.
• Control bus: bidirectional, carries control signals (read, write, clock, interrupt).
• All three buses work together to enable communication between the CPU and other components.

OCR Exam Tip: Be prepared to explain what each bus does and whether it is unidirectional or bidirectional. Also know how bus width affects performance.

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Worked Example: Reading from Memory Step by Step

One of the highest-value worked examples for OCR J277 is tracing a single memory read across the three buses. Once you can talk through this example cleanly, you can answer almost any bus-related exam question.

Scenario: The CPU needs to read the byte stored at memory address 42 into its Memory Data Register. The machine has a 16-bit address bus, an 8-bit data bus, and a control bus carrying at least READ, WRITE and CLOCK lines.

Step 1 — preparation inside the CPU. The Control Unit has already copied an address (42) from the PC or an instruction's operand into the MAR. The MAR is 16 bits wide, matching the address bus.

Step 2 — address bus activity. Because the address bus is 16 bits wide, 16 parallel wires run from the MAR to the memory controller. The binary representation of 42 (0000000000101010) is placed on these wires simultaneously. The address bus is unidirectional — signals travel only from the CPU outward — so memory cannot send anything back on these wires.

Step 3 — control bus activity. At the same time, the Control Unit asserts the READ line on the control bus (sets it to logic 1) and keeps the WRITE line at logic 0. The clock line provides a synchronising pulse so the memory controller samples the address at exactly the right moment.

Step 4 — memory responds. The memory controller decodes the 16-bit address, looks up the storage cell labelled 42, and fetches the 8-bit byte stored there. That byte is placed on the 8 wires of the data bus.

Step 5 — data bus activity. The data bus is bidirectional. During a read, signals flow from memory back into the CPU. The 8 bits arrive at the MDR and are latched on the next clock edge. The READ line is then lowered.