Systems Architecture Exam Practice

This lesson brings together all the topics from OCR J277 Section 1.1 (Systems Architecture) and provides exam-style questions with model answers. Use this to consolidate your knowledge and practise the skills needed for Paper 1.

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Key Topics to Revise

Before attempting the practice questions, ensure you are confident with:

Topic	Key Points
CPU purpose	Fetches, decodes, and executes instructions
Von Neumann architecture	Stored program concept; shared memory for data and instructions
Registers	PC, MAR, MDR, ACC — their purposes and how they interact
FDE cycle	Step-by-step process of fetching, decoding, and executing
CPU performance	Clock speed, cache size, number of cores
Embedded systems	Dedicated function, examples, advantages/disadvantages
Buses	Address (unidirectional), data (bidirectional), control (bidirectional)
Input devices	Keyboard, mouse, sensors, scanners, etc.
Output devices	Monitor, printer, speakers, actuators

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Exam Technique: Command Words

OCR uses specific command words that tell you what type of answer is expected:

Command Word	What to Do	Typical Marks
State	Give a brief, factual answer	1 mark
Identify	Name or select the correct item	1 mark
Describe	Give a detailed account of features or processes	2-4 marks
Explain	Give reasons or causes — say why or how	2-4 marks
Compare	Identify similarities and/or differences	2-4 marks
Discuss	Consider different aspects, advantages, and disadvantages	4-8 marks

OCR Exam Tip: Always match the depth of your answer to the number of marks available. A 1-mark question needs a brief answer; a 4-mark question needs detailed explanation.

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Practice Question 1: The FDE Cycle (4 marks)

Question: Describe the three stages of the fetch-decode-execute cycle, naming the registers involved at each stage.

Model Answer:

Fetch: The address in the Program Counter (PC) is copied to the Memory Address Register (MAR). The instruction at that address is fetched from memory and placed in the Memory Data Register (MDR). The PC is incremented by 1. [2 marks]

Decode: The Control Unit (CU) takes the instruction from the MDR and decodes it, splitting it into the opcode (operation) and operand (data/address). [1 mark]

Execute: The instruction is carried out. If it is a calculation, the ALU performs it and stores the result in the Accumulator (ACC). If it is a branch, the PC is updated to a new address. [1 mark]

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Practice Question 2: CPU Performance (3 marks)

Question: A games designer is choosing a new CPU. Explain how each of the following affects CPU performance: (a) Clock speed (b) Number of cores (c) Cache size

Model Answer:

(a) Clock speed determines how many FDE cycles the CPU completes per second. A higher clock speed (measured in GHz) means instructions are processed faster. [1 mark]

(b) Number of cores affects how many tasks can be processed simultaneously. Each core can execute its own FDE cycle independently, enabling parallel processing. However, not all software can use multiple cores effectively. [1 mark]

(c) Cache size determines how much frequently used data can be stored close to the CPU. Larger cache means more cache hits and fewer slow accesses to RAM, improving overall speed. [1 mark]

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Practice Question 3: Embedded Systems (4 marks)