Von Neumann Architecture

This lesson covers the Von Neumann architecture, including key registers and the stored program concept, as required by OCR J277 Section 1.1.1. Understanding this architecture is fundamental to explaining how modern computers work.

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The Stored Program Concept

Most modern computers are based on a design proposed by mathematician John von Neumann in 1945. The central idea is the stored program concept:

• Instructions (programs) and data are stored together in the same main memory (RAM).
• Instructions are fetched from memory one at a time and executed in sequence.
• The CPU uses a single set of buses to communicate with memory.

This was a revolutionary idea at the time. Before Von Neumann's proposal, computers had to be physically rewired to change the program they ran. With the stored program concept, simply loading different instructions into memory allows the same hardware to perform completely different tasks.

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Structure of Von Neumann Architecture

The Von Neumann architecture consists of these main components:

Component	Purpose
CPU	Processes instructions and data
Main memory (RAM)	Stores both instructions and data
System bus	Carries data, addresses, and control signals between CPU and memory
Input/Output (I/O)	Allows communication with external devices

Inside the CPU, the key components are:

• Arithmetic Logic Unit (ALU) — performs calculations and logical comparisons
• Control Unit (CU) — manages the FDE cycle and sends control signals
• Registers — small, fast storage locations for data the CPU is currently using

The following diagram shows how these components are connected:

graph TD
    subgraph CPU
        CU["Control Unit\n(CU)"]
        ALU["Arithmetic Logic Unit\n(ALU)"]
        REG["Registers\nPC | MAR | MDR | ACC"]
    end
    MEM["Main Memory\n(RAM)"]
    IO["Input/Output\nDevices"]
    CPU --- |"Data Bus"| MEM
    CPU --- |"Address Bus"| MEM
    CPU --- |"Control Bus"| MEM
    CPU --- IO
    CU --- ALU
    CU --- REG
    ALU --- REG

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Key Registers in Von Neumann Architecture

You must know these four registers for OCR J277:

Register	Full Name	Purpose
MAR	Memory Address Register	Holds the address of the memory location about to be read from or written to
MDR	Memory Data Register	Holds the data that has been fetched from memory, or data about to be written to memory
PC	Program Counter	Holds the address of the next instruction to be fetched
ACC	Accumulator	Stores the result of calculations performed by the ALU

How the Registers Work Together

1. The PC holds the address of the next instruction. This address is copied to the MAR.
2. The CPU sends a read signal along the control bus. The instruction at the address in the MAR is fetched from memory and placed in the MDR.
3. The CU decodes the instruction from the MDR.
4. If the instruction involves a calculation, the ALU performs it and stores the result in the ACC.
5. The PC is incremented so it points to the next instruction (unless a branch instruction changes it).

OCR Exam Tip: A very common exam question asks you to describe what happens during each stage of the FDE cycle, referencing specific registers. Practise writing this sequence using MAR, MDR, PC, and ACC.

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The Von Neumann Bottleneck

A well-known limitation of the Von Neumann architecture is the Von Neumann bottleneck:

• Because instructions and data share the same memory and bus, only one piece of data or one instruction can be transferred at a time.
• This creates a bottleneck — the CPU often has to wait for data to be fetched from memory before it can continue processing.
• Modern computers mitigate this with cache memory, pipelining, and multi-core processors, but the fundamental bottleneck remains.

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Von Neumann vs Harvard Architecture

While most general-purpose computers use Von Neumann architecture, some specialised systems use Harvard architecture:

Feature	Von Neumann	Harvard
Memory	Instructions and data share the same memory	Instructions and data have separate memory spaces
Buses	Single set of buses	Separate buses for instructions and data
Speed	Potential bottleneck	Can fetch instructions and data simultaneously
Use	General-purpose computers (PCs, laptops)	Embedded systems, DSP (digital signal processing)

OCR Exam Tip: OCR J277 focuses primarily on Von Neumann architecture, but you may be asked to compare it with Harvard architecture. Know that the key difference is whether instructions and data share memory.

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Worked Example: Following Registers Through an Instruction

Suppose the CPU is about to execute the instruction at memory address 0x1C (hex), which stores ADD #7 (add the literal value 7 to the accumulator). Before the instruction begins, the PC holds 0x1C and the ACC holds 0x05 (decimal 5).

Step	PC	MAR	MDR	ACC	Action
Start	0x1C	—	—	0x05	Ready to fetch
Fetch a	0x1C	0x1C	—	0x05	PC copied to MAR
Fetch b	0x1C	0x1C	ADD #7	0x05	Instruction loaded into MDR
Fetch c	0x1D	0x1C	ADD #7	0x05	PC incremented
Decode	0x1D	0x1C	ADD #7	0x05	CU identifies opcode ADD, operand 7
Execute	0x1D	0x1C	ADD #7	0x0C	ALU computes 5 + 7 = 12 = 0x0C, placed in ACC

Notice that the PC increments during the fetch stage — so by the time the instruction is being decoded, the PC already points to the next address. This is important because a branch instruction would overwrite the PC again during execute.

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Binary Example: What an Instruction Looks Like

A single instruction might be stored as a 16-bit binary value:

10010000 00000111

The opcode (first 8 bits) is 10010000. The CPU's instruction set defines 10010000 as ADD. The operand (last 8 bits) is 00000111, which is the decimal value 7. So the CPU decodes this as "add the number 7 to the accumulator".

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Misconception Callouts

Misconception: "The accumulator is a big memory chip." Correction: The ACC is a single register — typically 32 or 64 bits wide. It holds just one value at a time, the current intermediate result of ALU calculations.

Misconception: "Von Neumann and Harvard architectures are competitors — only one is used." Correction: Both are used widely. Von Neumann is dominant in general-purpose computers. Harvard is common in microcontrollers and digital signal processors (DSPs) where deterministic performance matters. Many modern CPUs use a modified Harvard design internally — separate L1 caches for instructions and data, but shared main memory.

Misconception: "The MAR holds the actual instruction." Correction: The MAR holds an address, not an instruction. The instruction or data at that address is moved into the MDR after the read completes.

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Mini-Challenge

Question: Explain why changing the PC during the execute stage is necessary for programs that contain loops or "if" statements.