The Fetch-Decode-Execute Cycle

This lesson provides a detailed examination of the fetch-decode-execute (FDE) cycle, which is the fundamental process by which the CPU carries out instructions. This is a core topic in OCR J277 Section 1.1.1.

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What Is the FDE Cycle?

The fetch-decode-execute cycle is the continuous process that the CPU repeats for every instruction it processes. The cycle has three stages:

1. Fetch — retrieve the next instruction from memory
2. Decode — interpret the instruction to determine what action is needed
3. Execute — carry out the instruction

This cycle repeats continuously from the moment the computer is powered on until it is shut down. A modern CPU operating at 3 GHz completes approximately 3 billion of these cycles every second.

The following diagram shows the continuous cycle the CPU follows:

graph LR
    F["1. FETCH\nRetrieve instruction\nfrom memory"] --> D["2. DECODE\nInterpret the\ninstruction"]
    D --> E["3. EXECUTE\nCarry out the\ninstruction"]
    E --> F

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Stage 1: Fetch

The purpose of the fetch stage is to retrieve the next instruction from main memory (RAM) and bring it into the CPU.

Step-by-step process:

1. The Program Counter (PC) holds the address of the next instruction to be fetched.
2. The address in the PC is copied to the Memory Address Register (MAR).
3. The CPU sends a read signal along the control bus to main memory.
4. The instruction stored at the address in the MAR is transferred along the data bus into the Memory Data Register (MDR).
5. The PC is incremented by 1 (so it now points to the next instruction in sequence).

At the end of the fetch stage, the instruction is stored in the MDR, ready to be decoded.

OCR Exam Tip: Remember the order: PC -> MAR -> Memory -> MDR. This sequence is often tested in exam questions that ask you to describe the fetch stage.

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Stage 2: Decode

The purpose of the decode stage is to interpret the instruction so the CPU knows what action to take.

Step-by-step process:

1. The instruction in the MDR is passed to the Control Unit (CU).
2. The CU splits the instruction into two parts:
   • Opcode — the operation to perform (e.g. ADD, LOAD, STORE, BRANCH)
   • Operand — the data value or memory address the operation acts on
3. The CU determines which components need to be activated (e.g. the ALU for a calculation, or memory for a data transfer).
4. The CU prepares the control signals that will be sent to the relevant components.

Example

Consider the instruction: ADD 5

Part	Value	Meaning
Opcode	ADD	Perform addition
Operand	5	Add the value 5 (or the value at memory address 5)

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