The Fetch-Decode-Execute Cycle

This lesson provides a detailed examination of the fetch-decode-execute (FDE) cycle, which is the fundamental process by which the CPU carries out instructions. This is a core topic in OCR J277 Section 1.1.1.

---

What Is the FDE Cycle?

The fetch-decode-execute cycle is the continuous process that the CPU repeats for every instruction it processes. The cycle has three stages:

1. Fetch — retrieve the next instruction from memory
2. Decode — interpret the instruction to determine what action is needed
3. Execute — carry out the instruction

This cycle repeats continuously from the moment the computer is powered on until it is shut down. A modern CPU operating at 3 GHz completes approximately 3 billion of these cycles every second.

The following diagram shows the continuous cycle the CPU follows:

graph LR
    F["1. FETCH\nRetrieve instruction\nfrom memory"] --> D["2. DECODE\nInterpret the\ninstruction"]
    D --> E["3. EXECUTE\nCarry out the\ninstruction"]
    E --> F

---

Stage 1: Fetch

The purpose of the fetch stage is to retrieve the next instruction from main memory (RAM) and bring it into the CPU.

Step-by-step process:

1. The Program Counter (PC) holds the address of the next instruction to be fetched.
2. The address in the PC is copied to the Memory Address Register (MAR).
3. The CPU sends a read signal along the control bus to main memory.
4. The instruction stored at the address in the MAR is transferred along the data bus into the Memory Data Register (MDR).
5. The PC is incremented by 1 (so it now points to the next instruction in sequence).

At the end of the fetch stage, the instruction is stored in the MDR, ready to be decoded.

OCR Exam Tip: Remember the order: PC -> MAR -> Memory -> MDR. This sequence is often tested in exam questions that ask you to describe the fetch stage.

---

Stage 2: Decode

The purpose of the decode stage is to interpret the instruction so the CPU knows what action to take.

Step-by-step process:

1. The instruction in the MDR is passed to the Control Unit (CU).
2. The CU splits the instruction into two parts:
   • Opcode — the operation to perform (e.g. ADD, LOAD, STORE, BRANCH)
   • Operand — the data value or memory address the operation acts on
3. The CU determines which components need to be activated (e.g. the ALU for a calculation, or memory for a data transfer).
4. The CU prepares the control signals that will be sent to the relevant components.

Example

Consider the instruction: ADD 5

Part	Value	Meaning
Opcode	ADD	Perform addition
Operand	5	Add the value 5 (or the value at memory address 5)

---

Stage 3: Execute

The purpose of the execute stage is to carry out the decoded instruction. What happens during execution depends on the type of instruction:

Arithmetic / Logic Operation

• The ALU performs the calculation (e.g. addition, comparison).
• The result is stored in the Accumulator (ACC).

Data Transfer

• Data is moved between registers, or between a register and main memory.
• For example, a LOAD instruction copies a value from memory into the ACC.
• A STORE instruction copies the value in the ACC to a memory location.

Branch Instruction

• The PC is changed to a new address (instead of simply being the next sequential address).
• This causes the CPU to jump to a different part of the program — used for loops and conditional statements.

---

The Complete Cycle — Traced Example

Suppose memory contains these instructions starting at address 100:

Address	Instruction
100	LOAD 50
101	ADD 51
102	STORE 52

Cycle 1: LOAD 50

• Fetch: PC=100 -> MAR=100 -> MDR=LOAD 50 -> PC incremented to 101
• Decode: CU identifies opcode LOAD, operand 50
• Execute: Value at memory address 50 is loaded into the ACC

Cycle 2: ADD 51

• Fetch: PC=101 -> MAR=101 -> MDR=ADD 51 -> PC incremented to 102
• Decode: CU identifies opcode ADD, operand 51
• Execute: ALU adds value at address 51 to the ACC, result stored in ACC

Cycle 3: STORE 52

• Fetch: PC=102 -> MAR=102 -> MDR=STORE 52 -> PC incremented to 103
• Decode: CU identifies opcode STORE, operand 52
• Execute: Value in ACC is written to memory address 52

---

The Role of the Clock

The FDE cycle is synchronised by the system clock, a component that generates a regular electrical pulse. Each pulse (or "tick") triggers the next step in the cycle.

• Clock speed is measured in Hertz (Hz) — the number of cycles per second.
• 1 GHz = 1 billion cycles per second.
• A higher clock speed means more FDE cycles per second, which generally means faster processing.

---

Summary

• The FDE cycle is the fundamental operation of the CPU (OCR J277 1.1.1).
• Fetch: PC -> MAR -> instruction fetched from memory -> MDR -> PC incremented.
• Decode: CU splits instruction into opcode and operand, prepares control signals.
• Execute: ALU performs calculations, data is moved, or the PC is changed for a branch.
• The system clock synchronises the cycle — higher clock speed means more cycles per second.

OCR Exam Tip: You may be asked to trace through the FDE cycle for a specific instruction. Practise writing out the step-by-step process using register names (PC, MAR, MDR, ACC).

---

Worked Example: Tracing a BRANCH Instruction

Most worked examples focus on ADD or LOAD. Branching is worth practising because it is the only instruction type that rewrites the PC during execute.

Suppose memory contains:

Address	Instruction
200	LOAD 300
201	CMP 0 (compare ACC with zero)
202	BRZ 210 (branch to 210 if ACC is zero)
203	ADD 301
...	...
210	STORE 302

Assume the value at address 300 is 0.

Cycle for BRZ 210:

• Fetch: PC = 202. MAR = 202. MDR = BRZ 210. PC is incremented to 203.
• Decode: The CU identifies opcode BRZ (branch if zero) and operand 210.
• Execute: The CU checks the zero flag set earlier by the CMP instruction. Because ACC is zero, the flag is set. The CU overwrites the PC with 210. The next fetch will now retrieve the instruction at address 210, skipping instruction 203 entirely.