OCR A-Level Computer Science: Boolean Algebra & Logic — Complete Revision Guide (H446)
OCR A-Level Computer Science: Boolean Algebra & Logic — Complete Revision Guide
Boolean algebra is the mathematics of true and false, and logic is how that mathematics becomes physical hardware. This module explains the logic gates from which every processor is built, the truth tables and algebraic laws that describe their behaviour, the techniques — including De Morgan's laws and Karnaugh maps — for simplifying logic to use fewer gates, and the combinational and sequential circuits that perform arithmetic and store state. It is the most self-contained and procedural area of OCR A-Level Computer Science (H446): the rules are few, exact and consistent, so with practice this module becomes a reliable source of full-mark answers.
In the H446 specification this material sits in module 1.4.3 (Boolean algebra) and is examined in Component 01: Computer Systems. The questions are recognisable and recurring: complete or interpret a truth table for a given gate or circuit; write the Boolean expression a logic diagram represents (or draw the diagram for an expression); simplify an expression using the Boolean laws or De Morgan's laws; use a Karnaugh map to minimise a function; and explain the operation of standard building blocks such as the half adder, full adder and D-type flip-flop. The examiner rewards exact notation and shown working — a simplification that states which law is applied at each step is far stronger than an unexplained jump to the answer.
This is Course 4 of 11 on the LearningBro OCR A-Level Computer Science learning path. The course, Boolean Algebra & Logic, opens with logic gates and truth tables, develops the Boolean laws, De Morgan's laws and the simplification techniques that culminate in Karnaugh maps, then applies them to logic circuits, adders and flip-flops, closing with circuit design. It is the hardware counterpart to the binary arithmetic of Data Representation and rests on the processor model from Processors & Hardware.
Guide Overview
The Boolean Algebra & Logic course is built as ten lessons that move from logic gates and truth tables through the Boolean laws and simplification techniques into Karnaugh maps, then apply the algebra to logic circuits, adders and sequential flip-flops, closing on circuit design.
- Logic Gates
- Truth Tables
- Boolean Algebra Laws
- De Morgan's Laws
- Simplifying Boolean Expressions
- Karnaugh Maps
- Logic Circuits
- Half Adders and Full Adders
- Flip-Flops
- Circuit Design
Logic Gates
The logic gates lesson establishes the building blocks of all digital logic. H446 expects fluency with six gates: NOT (inverts a single input), AND (output 1 only when all inputs are 1), OR (output 1 when at least one input is 1), XOR (exclusive OR, output 1 when the inputs differ), NAND (the inverse of AND) and NOR (the inverse of OR). Each has a standard symbol you must recognise and draw, and a standard Boolean notation: a dot or juxtaposition for AND, a plus for OR, a bar or prime for NOT, and a circled plus for XOR.
The conceptual point worth carrying forward is the functional completeness of NAND and NOR: any logic function whatsoever can be built from NAND gates alone, or from NOR gates alone, which is why these gates are so important in real hardware. This is the lesson to over-learn first, because every later lesson — truth tables, simplification, circuits, adders — assumes instant recall of what each gate does and how it is written.
| Gate | Notation | Output is 1 when |
|---|---|---|
| NOT A | A with bar / A' | A is 0 |
| A AND B | A.B | both A and B are 1 |
| A OR B | A + B | A or B (or both) is 1 |
| A XOR B | A (+) B | A and B differ |
| A NAND B | (A.B)' | NOT both are 1 |
| A NOR B | (A + B)' | neither is 1 |
Truth Tables
The truth tables lesson develops the systematic tool for describing exactly what a gate or circuit does for every possible combination of inputs. A truth table lists all 2^n input combinations for n inputs and the resulting output, and the disciplined habit examiners reward is to enumerate the input rows in a fixed binary-counting order (00, 01, 10, 11 for two inputs) so that no combination is missed.
The lesson teaches the two core moves: building the truth table for a multi-gate circuit by adding a column for each intermediate signal and working left to right, and reading a Boolean expression off a completed truth table by taking the rows where the output is 1. This second move — deriving the sum-of-products expression from a truth table — is the bridge to simplification, because that raw expression is usually far larger than it needs to be. Truth tables are also the standard way to prove two expressions equivalent: build both and check the output columns match, a technique reused to verify simplifications and De Morgan's laws.
Boolean Algebra Laws
The Boolean algebra laws lesson develops the algebraic identities that let you manipulate and simplify expressions without drawing a truth table each time. The laws H446 examines parallel ordinary algebra but include identities unique to Boolean logic.
| Law | Form |
|---|---|
| Identity | A.1 = A; A + 0 = A |
| Null (annulment) | A.0 = 0; A + 1 = 1 |
| Idempotent | A.A = A; A + A = A |
| Complement | A.A' = 0; A + A' = 1 |
| Double negation | (A')' = A |
| Commutative | A.B = B.A; A + B = B + A |
| Associative | A.(B.C) = (A.B).C |
| Distributive | A.(B + C) = A.B + A.C |
| Absorption | A + A.B = A; A.(A + B) = A |
The examinable skill is recognising which law applies at each step of a simplification and stating it. The absorption and complement laws in particular are where the biggest reductions come from, and the distributive law (which, unusually, works both ways in Boolean algebra) is the workhorse for factoring expressions toward a simpler form. This algebraic toolkit feeds directly into the simplifying Boolean expressions lesson.
De Morgan's Laws
The De Morgan's laws lesson develops the two transformations that handle the negation of compound expressions — the part of Boolean algebra students most often get wrong, and therefore a reliable discriminator in the exam. The laws state that the complement of an AND is the OR of the complements, and the complement of an OR is the AND of the complements:
(A.B)' = A' + B'
(A + B)' = A'.B'
The practical rule to internalise is "break the bar and change the sign": when you split a NOT across a bracket, AND becomes OR (and vice versa) and each variable is individually complemented. De Morgan's laws are essential for two recurring tasks: simplifying expressions that contain a negated bracket, and converting a design into NAND-only or NOR-only form (exploiting the functional completeness noted in the logic gates lesson). Verify any application by truth table until the transformation is second nature.
Simplifying Boolean Expressions
The simplifying Boolean expressions lesson brings the laws together into the procedural skill the exam tests most directly: taking a complicated expression — typically the raw sum-of-products read off a truth table — and reducing it to the fewest terms, which in hardware means the fewest gates. The disciplined method is to apply the laws one step at a time, writing the simplified expression and naming the law used at each step, so that the working tells a clear story and earns method marks even if a slip occurs.
The high-value moves are factoring with the distributive law, eliminating terms with the complement and absorption laws, and using De Morgan's laws to clear negated brackets. Why this matters in engineering terms is a recurring extended-answer point: a simpler expression needs fewer gates, which reduces cost, power consumption, physical space and propagation delay in the final circuit. This algebraic route to minimisation is then complemented by the visual method in the next lesson, and the two are alternative tools for the same job.
Karnaugh Maps
The Karnaugh maps lesson develops the graphical technique for minimising a Boolean function of up to four variables without algebra. A Karnaugh map is a grid with one cell per input combination, arranged so that adjacent cells differ in exactly one variable — which is why the rows and columns are labelled in Gray code (00, 01, 11, 10) rather than ordinary binary order. You plot a 1 in every cell where the function is true, then group the 1s.
The rules for grouping are precise and examinable: groups must be rectangular and contain a number of cells that is a power of two (1, 2, 4, 8); groups should be as large as possible (a larger group eliminates more variables); every 1 must be covered by at least one group; groups may overlap; and the map wraps around, so cells on opposite edges (and the four corners) are adjacent. Each group then yields one product term containing only the variables that stay constant across it, and the simplified expression is the OR of these terms. The Karnaugh map often reaches a minimal form faster and more reliably than algebra, which is exactly why H446 teaches it alongside the algebraic simplification — practise reading the minimal expression off the groups until it is routine.
Logic Circuits
The logic circuits lesson develops the two-way translation between a Boolean expression and a combinational logic diagram — a circuit whose output depends only on its current inputs. Given an expression you draw the gates that implement it, wiring inputs through AND, OR, NOT and XOR gates to the output; given a diagram you trace the signals through each gate to write the expression and, if asked, build its truth table.
The lesson stresses the standard workflow that ties the whole module together: derive an expression (often from a truth table or a worded specification), simplify it with the laws or a Karnaugh map, then draw the minimised circuit — because a simplified expression produces a smaller, cheaper, faster circuit. A combinational circuit has no memory: the same inputs always give the same output, with no dependence on past values. That limitation is precisely what motivates the sequential circuits — the flip-flops — introduced later, which can store state.
Half Adders and Full Adders
The half adders and full adders lesson applies combinational logic to binary arithmetic, connecting this module directly to the binary arithmetic of the data-representation course. A half adder adds two single bits and produces a sum and a carry: the sum is the XOR of the inputs (1 when the bits differ) and the carry is the AND of the inputs (1 only when both are 1). It is "half" an adder because it cannot accept a carry coming in from a previous column.
A full adder adds three bits — two operand bits and a carry-in — producing a sum and a carry-out, and so can be chained: connecting the carry-out of each full adder to the carry-in of the next builds a ripple-carry adder that adds multi-bit numbers, which is the arithmetic engine inside the ALU described in Processors & Hardware. The examinable requirements are to give the sum and carry expressions, complete the truth tables for both adders, and explain how full adders are cascaded to add wider numbers. This is the clearest single example in the course of abstract Boolean algebra becoming working hardware.
Flip-Flops
The flip-flops lesson introduces sequential logic — circuits whose output depends not only on current inputs but also on stored state — and so explains how computers remember a single bit. A flip-flop is a bistable circuit with two stable states (storing 0 or 1) built from cross-coupled gates with feedback, where the output is fed back into the input so the circuit holds its value until told to change.
H446 examines the D-type flip-flop, which captures the value on its data input D and transfers it to the output on the active edge of a clock pulse, holding it until the next clock edge. This clocked, edge-triggered behaviour is what makes the D-type the basic storage element for registers and memory, linking back to the registers of Processors & Hardware. The key contrast to be able to articulate is combinational versus sequential: combinational circuits (gates, adders) have no memory and respond instantly to inputs, while sequential circuits (flip-flops) store state and are synchronised by a clock signal.
Circuit Design
The circuit design lesson consolidates the whole module into the end-to-end design process the exam ultimately tests: turning a worded problem into a minimal working circuit. The workflow is to define the inputs and the desired output behaviour, build a truth table capturing the specification, read off the sum-of-products expression, minimise it using the Boolean laws or a Karnaugh map, and then draw the gate diagram for the simplified expression.
The recurring assessment pattern is a short scenario — a safety interlock, a voting system, a simple controller — that you must realise as a circuit, demonstrating each stage of the process. The marks reward a complete, ordered method: a correct truth table, a valid simplification with the technique shown, and a circuit diagram that matches the minimised expression. This is where logic gates, truth tables, the algebraic laws, De Morgan's laws and Karnaugh maps all come together in a single answer, which is exactly why circuit design closes the course.
Worked Example: Simplifying with the Boolean Laws
Reading about the laws is not the same as being able to drive them under exam pressure, so here is a full simplification with the law named at every step — exactly the layout the examiner rewards. The task is to simplify the expression A.B+A.B′+A′.B, a typical raw sum-of-products of the kind you read off a truth table.
A.B + A.B' + A'.B (start)
= A.(B + B') + A'.B distributive law (factor A from first two terms)
= A.1 + A'.B complement law (B + B' = 1)
= A + A'.B identity law (A.1 = A)
= (A + A').(A + B) distributive law (the second, Boolean-only form)
= 1.(A + B) complement law (A + A' = 1)
= A + B identity law (1.(A + B) = A + B)
The result, A+B, is a single OR gate where the original needed three AND gates, two inverters and an OR — a dramatic hardware saving. Two moves in this working are worth internalising because they recur constantly. The first is factoring out a common variable so that a complement pair (B+B′) collapses to 1. The second is the redundancy-elimination identity A+A′.B=A+B, which is one of the most useful shortcuts in the whole topic and is itself provable from the distributive and complement laws as shown above. If you memorise A+A′.B=A+B (and its dual A.(A′+B)=A.B) you will spot reductions that otherwise stay hidden.
A note on discipline that separates a top-band answer from a middling one: write one transformation per line and name the law. If your arithmetic slips at line four, an examiner following a clearly labelled derivation can still award the method marks for lines one to three and five onwards. A student who leaps from the starting expression straight to A+B with no working earns full marks only if the answer is perfect and nothing if it is not — the shown method is an insurance policy as much as a communication.
Worked Example: Applying De Morgan's Laws
De Morgan's laws are the single most common source of sign errors in this module, so a worked application earns its place. Simplify (A.B+C)′ — a negated bracket containing both an AND and an OR, which is precisely the shape that trips students up.
(A.B + C)' (start)
= (A.B)'.(C)' De Morgan (complement of an OR is AND of complements)
= (A' + B').C' De Morgan again (complement of the inner AND) + double negation on C
The crucial habit is to peel one bar at a time from the outside in. The outermost operation inside the bracket is the OR between A.B and C, so the first De Morgan step turns that OR into an AND and complements each side, giving (A.B)′.C′. Only then do you apply De Morgan a second time to the inner (A.B)′, which becomes A′+B′. A student who tries to distribute the bar across everything in one move typically produces A′.B′+C′, which is wrong — a truth table would show the output columns do not match. When in doubt, verify by building the truth table for both the original and your answer; if the output columns are identical, the transformation is sound.
De Morgan's laws are also the mechanism behind converting any circuit to NAND-only or NOR-only form, exploiting the functional completeness noted earlier. To realise A+B using only NAND gates, for instance, note that A+B=(A′.B′)′=(A′)′ NAND (B′)′ after a double-negation, so two NAND-as-inverters feed a third NAND. Being able to justify such a conversion in words — "any AND-OR-NOT circuit can be redrawn in NAND-only form because NAND is functionally complete, which lets a factory use a single gate type" — is a reliable extended-answer point.
Worked Example: Minimising with a Karnaugh Map
Take the function of three variables that is true for the input combinations A′B′C, A′BC, AB′C and ABC (in decimal minterms, cells 1, 3, 5 and 7 — every row where C=1). Plotting these 1s onto a three-variable Karnaugh map with A across the top and BC down the side, using Gray-code ordering, gives a column of four 1s wherever C=1.
That block of four cells is a single valid group: it is rectangular, its size is a power of two, and it is as large as possible. Across the group, only C stays constant (at 1) while both A and B take every value, so both A and B are eliminated and the group yields the single term C. The minimised function is simply F=C — the output depends on C alone. Verifying algebraically confirms it: A′B′C+A′BC+AB′C+ABC=C.(A′B′+A′B+AB′+AB)=C.1=C.
The exam-relevant lessons from this example are, first, that bigger groups eliminate more variables — a group of four kills two variables, a group of eight kills three — so you should always chase the largest legal grouping before settling for smaller ones. Second, remember the map wraps around: cells on the left and right edges are adjacent, as are the top and bottom rows, and in a four-variable map the four corners form a legal group of four. A group that looks split across the edges of the grid is often the key to the minimal answer, and candidates who forget the wrap-around routinely miss it and hand in a larger-than-necessary expression.
| K-map grouping rule | Why it matters |
|---|---|
| Group size must be a power of two (1, 2, 4, 8) | Only powers of two eliminate whole variables cleanly |
| Make each group as large as legally possible | A larger group removes more variables, giving fewer literals |
| Every 1 must be in at least one group | An uncovered 1 means the expression is wrong (too restrictive) |
| Groups may overlap | Reusing a 1 in two groups is allowed and often necessary for maximal groups |
| The map wraps (edges and corners are adjacent) | The minimal group is frequently split across opposite edges |
Worked Example: The Half Adder and Full Adder
The half adder is the neatest bridge from Boolean algebra to arithmetic hardware. Adding two single bits A and B produces a sum and a carry. Enumerating all four input rows: 0+0=00, 0+1=01, 1+0=01, and 1+1=10. Reading the sum column, it is 1 exactly when the inputs differ — that is XOR — and reading the carry column, it is 1 only when both inputs are 1 — that is AND. Hence:
Sum = A (+) B (XOR)
Carry = A.B (AND)
The half adder cannot accept a carry in from a lower column, which is why real multi-bit addition needs the full adder, taking three inputs — A, B and a carry-in Cin — and producing a sum and a carry-out. Its Boolean expressions are:
Sum = A (+) B (+) Cin
Cout = A.B + Cin.(A (+) B)
The sum is 1 when an odd number of the three inputs is 1 (the three-input XOR), and the carry-out is 1 whenever at least two of the three inputs are 1. A common way to build a full adder is from two half adders and an OR gate: the first half adder adds A and B; the second adds that partial sum to Cin; and the two carry outputs are OR-ed to form Cout. Cascading full adders — wiring each carry-out into the next stage's carry-in — produces a ripple-carry adder that adds multi-bit numbers, the arithmetic engine inside the ALU. Examiners frequently ask you to complete the eight-row full-adder truth table, so rehearse it until you can reproduce it from the two expressions above without hesitation.
Common Mistakes and How to Avoid Them
Certain errors recur across this module year after year, and knowing them in advance is worth several marks.
- Mis-applying De Morgan's laws. The classic slip is (A+B)′=A′+B′ (wrong) instead of A′.B′ (right). Remember: break the bar, change the operator. An AND under a bar becomes an OR of complements and vice versa.
- Confusing XOR with OR. OR is true when at least one input is 1 (including both); XOR is true only when the inputs differ. In the half adder the sum is XOR, not OR — a student who writes A+B for the sum gets 1+1=1 where the correct sum bit is 0.
- Wrong truth-table row order. Enumerate inputs in strict binary-counting order (000, 001, 010, 011, …). Skipping or reordering rows is the easiest way to derive a wrong expression from a correct circuit.
- Illegal Karnaugh groups. Groups of three cells, or L-shaped groups, are not allowed — only rectangular blocks whose size is a power of two. Forgetting the wrap-around is the other frequent K-map error.
- Unexplained simplification jumps. Even when the final answer is right, leaping several steps without naming laws forfeits method marks if any slip creeps in. One line, one law.
- Forgetting the double-negation clean-up. After a De Morgan step, terms like (C′)′ must be reduced to C; leaving stray double bars produces an untidy, sometimes wrong-looking expression.
Exam Technique for Boolean Questions
Because this material is procedural, the exam rewards a rehearsed routine over improvisation. When a question hands you a circuit diagram, trace each gate output as a labelled intermediate signal before attempting the overall expression — this converts a daunting multi-gate diagram into a sequence of trivial single-gate reads. When a question asks you to simplify, always show the law at each step; when it asks you to draw, minimise first so your diagram uses the fewest gates. If a question specifies NAND-only or NOR-only implementation, expect to use De Morgan's laws and double-negation, and say so explicitly.
Watch the command words. Complete the truth table is pure enumeration — do every row. Simplify expects an algebraic derivation or a Karnaugh map with the working shown. Explain the operation of a half adder or flip-flop wants the behaviour in words (what each output represents, what triggers a change), not just an expression. And design a circuit for a scenario expects the full pipeline: define inputs and outputs, build the truth table, read the sum-of-products, minimise, then draw. Allocate your time in proportion to the marks, and never leave a truth table half-completed — every correct row is a potential mark.
Mini-FAQ
Do I need to memorise all the Boolean laws? Yes — the identity, null, idempotent, complement, double-negation, commutative, associative, distributive and absorption laws, plus both De Morgan's laws, are all fair game and you cannot look them up in the exam. Drill them until you can reproduce the table from memory, and specifically over-learn the two redundancy identities A+A′.B=A+B and A.(A′+B)=A.B, which unlock reductions that are otherwise easy to miss.
When should I use a Karnaugh map instead of algebra? Both are legitimate and reach the same minimal answer. Karnaugh maps are usually faster and less error-prone for functions of three or four variables read off a truth table, because grouping is visual and mechanical. Algebra is better when you are handed an expression rather than a truth table, or when the function has more than four variables (beyond the practical reach of a hand-drawn K-map). If a question says "use algebra" or "use a Karnaugh map", follow the instruction; otherwise pick the tool that suits the input.
What is the difference between combinational and sequential logic? A combinational circuit's output depends only on its current inputs — gates, adders and any circuit built purely from them. A sequential circuit's output depends on both current inputs and stored state, and it is typically synchronised by a clock; flip-flops are the standard example. The single-sentence discriminator examiners want is that combinational logic has no memory and responds instantly, while sequential logic stores state and changes on a clock edge.
Why are NAND and NOR called "functionally complete"? Because any Boolean function whatsoever can be built using only NAND gates, or only NOR gates. This matters in real manufacturing: a chip built from a single gate type is cheaper and simpler to fabricate and test. Being able to convert an AND-OR-NOT design into NAND-only form using De Morgan's laws is the examinable consequence of this property.
How to Revise Boolean Algebra & Logic
This module is procedural, so the most effective revision is repeated practice of the exam moves rather than rereading definitions. Make sure you can, from memory, draw and recognise all six gate symbols and write their notation; complete a truth table in correct binary-counting order; quote the Boolean laws and De Morgan's laws; and simplify an expression while naming the law at each step. These are the recall foundations on which every question rests, and they are quick to over-learn.
Then drill the two minimisation routes — algebraic simplification and Karnaugh maps — on a steady supply of expressions, because almost every Boolean question reduces to "simplify this, then draw or interpret the circuit". Pay particular attention to the standard building blocks, since the half adder, full adder and D-type flip-flop appear repeatedly: be able to state their sum/carry or data/clock behaviour, complete their truth tables, and explain how adders cascade and how a flip-flop stores a bit. Working a handful of full design problems end to end — truth table, minimisation, diagram — is the single best preparation for the extended-answer items.
Start at the Boolean Algebra & Logic course and work through all ten lessons in order, from logic gates to circuit design. Once the gates, laws and minimisation techniques are fluent, the adders tie straight back to the binary arithmetic of the data-representation course and the flip-flops to the registers of Processors & Hardware, completing the hardware foundation of the OCR A-Level Computer Science path.
Related Reading
- OCR A-Level Computer Science: Data Representation — Complete Revision Guide — the binary-arithmetic partner to this module; the half and full adders here are the hardware that performs that arithmetic.
- OCR A-Level Computer Science: Processors & Hardware — Complete Revision Guide — where the ALU, registers and clock that use adders and flip-flops are examined in context.
- OCR A-Level Computer Science: Exam Preparation — Complete Revision Guide — how Boolean questions are marked on Paper 1 and how to structure a full-marks simplification.
- Boolean Algebra & Logic course — the ten-lesson course this guide summarises.
- Data Representation course — number systems, two's complement and floating point.
- Processors & Hardware course — CPU architecture, the fetch-decode-execute cycle and performance factors.